ASoC: fsi: tidyup: move fsi_fifo_init() onto fsi_hw_startup()
fsi_fifo_init() is called only from fsi_hw_startup() Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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1 changed files with 54 additions and 55 deletions
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@ -692,61 +692,6 @@ static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable)
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/*
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/*
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* ctrl function
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* ctrl function
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*/
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*/
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static void fsi_fifo_init(struct fsi_priv *fsi,
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int is_play,
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struct device *dev)
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{
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struct fsi_master *master = fsi_get_master(fsi);
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struct fsi_stream *io = fsi_stream_get(fsi, is_play);
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u32 shift, i;
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int frame_capa;
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/* get on-chip RAM capacity */
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shift = fsi_master_read(master, FIFO_SZ);
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shift >>= fsi_get_port_shift(fsi, is_play);
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shift &= FIFO_SZ_MASK;
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frame_capa = 256 << shift;
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dev_dbg(dev, "fifo = %d words\n", frame_capa);
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/*
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* The maximum number of sample data varies depending
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* on the number of channels selected for the format.
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*
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* FIFOs are used in 4-channel units in 3-channel mode
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* and in 8-channel units in 5- to 7-channel mode
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* meaning that more FIFOs than the required size of DPRAM
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* are used.
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*
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* ex) if 256 words of DP-RAM is connected
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* 1 channel: 256 (256 x 1 = 256)
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* 2 channels: 128 (128 x 2 = 256)
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* 3 channels: 64 ( 64 x 3 = 192)
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* 4 channels: 64 ( 64 x 4 = 256)
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* 5 channels: 32 ( 32 x 5 = 160)
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* 6 channels: 32 ( 32 x 6 = 192)
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* 7 channels: 32 ( 32 x 7 = 224)
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* 8 channels: 32 ( 32 x 8 = 256)
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*/
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for (i = 1; i < fsi->chan_num; i <<= 1)
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frame_capa >>= 1;
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dev_dbg(dev, "%d channel %d store\n",
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fsi->chan_num, frame_capa);
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io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
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/*
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* set interrupt generation factor
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* clear FIFO
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*/
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if (is_play) {
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fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
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fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
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} else {
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fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
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fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
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}
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}
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static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, struct fsi_stream *io,
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static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, struct fsi_stream *io,
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void (*run16)(struct fsi_priv *fsi, int size),
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void (*run16)(struct fsi_priv *fsi, int size),
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void (*run32)(struct fsi_priv *fsi, int size),
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void (*run32)(struct fsi_priv *fsi, int size),
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@ -867,6 +812,60 @@ static irqreturn_t fsi_interrupt(int irq, void *data)
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/*
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/*
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* dai ops
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* dai ops
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*/
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*/
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static void fsi_fifo_init(struct fsi_priv *fsi,
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int is_play,
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struct device *dev)
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{
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struct fsi_master *master = fsi_get_master(fsi);
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struct fsi_stream *io = fsi_stream_get(fsi, is_play);
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u32 shift, i;
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int frame_capa;
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/* get on-chip RAM capacity */
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shift = fsi_master_read(master, FIFO_SZ);
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shift >>= fsi_get_port_shift(fsi, is_play);
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shift &= FIFO_SZ_MASK;
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frame_capa = 256 << shift;
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dev_dbg(dev, "fifo = %d words\n", frame_capa);
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/*
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* The maximum number of sample data varies depending
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* on the number of channels selected for the format.
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*
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* FIFOs are used in 4-channel units in 3-channel mode
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* and in 8-channel units in 5- to 7-channel mode
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* meaning that more FIFOs than the required size of DPRAM
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* are used.
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*
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* ex) if 256 words of DP-RAM is connected
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* 1 channel: 256 (256 x 1 = 256)
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* 2 channels: 128 (128 x 2 = 256)
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* 3 channels: 64 ( 64 x 3 = 192)
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* 4 channels: 64 ( 64 x 4 = 256)
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* 5 channels: 32 ( 32 x 5 = 160)
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* 6 channels: 32 ( 32 x 6 = 192)
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* 7 channels: 32 ( 32 x 7 = 224)
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* 8 channels: 32 ( 32 x 8 = 256)
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*/
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for (i = 1; i < fsi->chan_num; i <<= 1)
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frame_capa >>= 1;
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dev_dbg(dev, "%d channel %d store\n",
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fsi->chan_num, frame_capa);
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io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
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/*
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* set interrupt generation factor
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* clear FIFO
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*/
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if (is_play) {
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fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
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fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
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} else {
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fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
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fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
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}
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}
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static int fsi_hw_startup(struct fsi_priv *fsi,
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static int fsi_hw_startup(struct fsi_priv *fsi,
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int is_play,
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int is_play,
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