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mtd: eLBC NAND: increase bus timeout to maximum

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When a NAND operation is in progress, all other localbus operations
(including NOR flash) will have to wait for access to the bus.  However, the
NAND operation may take longer to complete than the default timeout.  Thus,
if NOR is accessed while a NAND operation is in progress, the NAND operation
will fail.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Scott Wood 2009-11-13 14:12:16 -06:00 committed by David Woodhouse
parent 54c69cc250
commit b3a70f0bc3
1 changed files with 7 additions and 0 deletions
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7
drivers/mtd/nand/fsl_elbc_nand.c
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@ -946,6 +946,13 @@ static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
{ {
struct fsl_lbc_regs __iomem *lbc = ctrl->regs; struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/*
* NAND transactions can tie up the bus for a long time, so set the
* bus timeout to max by clearing LBCR[BMT] (highest base counter
* value) and setting LBCR[BMTPS] to the highest prescaler value.
*/
clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15);
/* clear event registers */ /* clear event registers */
setbits32(&lbc->ltesr, LTESR_NAND_MASK); setbits32(&lbc->ltesr, LTESR_NAND_MASK);
out_be32(&lbc->lteatr, 0); out_be32(&lbc->lteatr, 0);