[PATCH] defxx: Big-endian hosts support
The PDQ DMA engine requires a different byte-swapping mode for big-endian hosts; also the MAC address which is read from a register through PIO has to be byte-swapped. These changes have been verified with DEFPA-DC (PCI) boards and a Broadcom BCM91250A (MIPS CPU based) host. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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2 changed files with 31 additions and 23 deletions
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@ -192,6 +192,7 @@
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* 04 Aug 2003 macro Converted to the DMA API.
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* 14 Aug 2004 macro Fix device names reported.
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* 14 Jun 2005 macro Use irqreturn_t.
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* 23 Oct 2006 macro Big-endian host support.
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*/
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/* Include files */
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@ -218,8 +219,8 @@
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/* Version information string should be updated prior to each new release! */
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#define DRV_NAME "defxx"
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#define DRV_VERSION "v1.08"
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#define DRV_RELDATE "2005/06/14"
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#define DRV_VERSION "v1.09"
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#define DRV_RELDATE "2006/10/23"
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static char version[] __devinitdata =
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DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
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@ -859,6 +860,7 @@ static int __devinit dfx_driver_init(struct net_device *dev,
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print_name);
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return(DFX_K_FAILURE);
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}
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data = cpu_to_le32(data);
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memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32));
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if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
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@ -867,6 +869,7 @@ static int __devinit dfx_driver_init(struct net_device *dev,
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print_name);
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return(DFX_K_FAILURE);
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}
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data = cpu_to_le32(data);
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memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16));
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/*
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@ -1085,27 +1088,23 @@ static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
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}
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/*
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* Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
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* Set the base address of Descriptor Block and bring adapter
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* to DMA_AVAILABLE state.
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*
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* Note: We also set the literal and data swapping requirements in this
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* command. Since this driver presently runs on Intel platforms
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* which are Little Endian, we'll tell the adapter to byte swap
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* data only. This code will need to change when we support
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* Big Endian systems (eg. PowerPC).
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* Note: We also set the literal and data swapping requirements
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* in this command.
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*
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* Assumption: 32-bit physical address of descriptor block is 8Kbyte
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* aligned. That is, bits 0-12 of the address must be zero.
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* Assumption: 32-bit physical address of descriptor block
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* is 8Kbyte aligned.
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*/
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if (dfx_hw_port_ctrl_req(bp,
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PI_PCTRL_M_INIT,
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(u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA),
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0,
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NULL) != DFX_K_SUCCESS)
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{
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printk("%s: Could not set descriptor block address!\n", bp->dev->name);
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return(DFX_K_FAILURE);
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}
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if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
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(u32)(bp->descr_block_phys |
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PI_PDATA_A_INIT_M_BSWAP_INIT),
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0, NULL) != DFX_K_SUCCESS) {
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printk("%s: Could not set descriptor block address!\n",
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bp->dev->name);
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return DFX_K_FAILURE;
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}
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/* Set transmit flush timeout value */
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@ -25,6 +25,7 @@
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* macros to DEFXX.C.
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* 12-Sep-96 LVS Removed packet request header pointers.
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* 04 Aug 2003 macro Converted to the DMA API.
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* 23 Oct 2006 macro Big-endian host support.
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*/
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#ifndef _DEFXX_H_
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@ -1344,7 +1345,7 @@ typedef struct
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/* Register definition structures are defined for both big and little endian systems */
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#ifndef BIG_ENDIAN
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#ifndef __BIG_ENDIAN
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/* Little endian format of Type 1 Producer register */
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@ -1402,7 +1403,11 @@ typedef union
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} index;
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} PI_TYPE_2_CONSUMER;
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#else
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/* Define swapping required by DMA transfers. */
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#define PI_PDATA_A_INIT_M_BSWAP_INIT \
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(PI_PDATA_A_INIT_M_BSWAP_DATA)
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#else /* __BIG_ENDIAN */
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/* Big endian format of Type 1 Producer register */
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@ -1460,7 +1465,11 @@ typedef union
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} index;
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} PI_TYPE_2_CONSUMER;
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#endif /* #ifndef BIG_ENDIAN */
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/* Define swapping required by DMA transfers. */
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#define PI_PDATA_A_INIT_M_BSWAP_INIT \
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(PI_PDATA_A_INIT_M_BSWAP_DATA | PI_PDATA_A_INIT_M_BSWAP_LITERAL)
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#endif /* __BIG_ENDIAN */
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/* Define EISA controller register offsets */
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