[TG3]: Add 5709 self-test support.
Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
715116a126
commit
b16250e3d1
2 changed files with 111 additions and 16 deletions
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@ -3615,8 +3615,7 @@ static irqreturn_t tg3_test_isr(int irq, void *dev_id,
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if ((sblk->status & SD_STATUS_UPDATED) ||
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!(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
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tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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0x00000001);
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tg3_disable_ints(tp);
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return IRQ_RETVAL(1);
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}
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return IRQ_RETVAL(0);
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@ -6860,8 +6859,7 @@ static int tg3_request_irq(struct tg3 *tp)
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static int tg3_test_interrupt(struct tg3 *tp)
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{
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struct net_device *dev = tp->dev;
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int err, i;
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u32 int_mbox = 0;
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int err, i, intr_ok = 0;
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if (!netif_running(dev))
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return -ENODEV;
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@ -6882,10 +6880,18 @@ static int tg3_test_interrupt(struct tg3 *tp)
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HOSTCC_MODE_NOW);
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for (i = 0; i < 5; i++) {
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u32 int_mbox, misc_host_ctrl;
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int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
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TG3_64BIT_REG_LOW);
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if (int_mbox != 0)
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misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
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if ((int_mbox != 0) ||
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(misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
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intr_ok = 1;
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break;
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}
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msleep(10);
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}
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@ -6898,7 +6904,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
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if (err)
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return err;
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if (int_mbox != 0)
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if (intr_ok)
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return 0;
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return -EIO;
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@ -8288,6 +8294,8 @@ static void tg3_get_ethtool_stats (struct net_device *dev,
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#define NVRAM_TEST_SIZE 0x100
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#define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
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#define NVRAM_SELFBOOT_HW_SIZE 0x20
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#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
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static int tg3_test_nvram(struct tg3 *tp)
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{
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@ -8299,12 +8307,14 @@ static int tg3_test_nvram(struct tg3 *tp)
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if (magic == TG3_EEPROM_MAGIC)
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size = NVRAM_TEST_SIZE;
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else if ((magic & 0xff000000) == 0xa5000000) {
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else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
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if ((magic & 0xe00000) == 0x200000)
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size = NVRAM_SELFBOOT_FORMAT1_SIZE;
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else
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return 0;
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} else
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} else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
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size = NVRAM_SELFBOOT_HW_SIZE;
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else
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return -EIO;
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buf = kmalloc(size, GFP_KERNEL);
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@ -8323,7 +8333,8 @@ static int tg3_test_nvram(struct tg3 *tp)
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goto out;
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/* Selfboot format */
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if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC) {
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if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
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TG3_EEPROM_MAGIC_FW) {
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u8 *buf8 = (u8 *) buf, csum8 = 0;
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for (i = 0; i < size; i++)
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@ -8338,6 +8349,51 @@ static int tg3_test_nvram(struct tg3 *tp)
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goto out;
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}
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if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
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TG3_EEPROM_MAGIC_HW) {
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u8 data[NVRAM_SELFBOOT_DATA_SIZE];
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u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
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u8 *buf8 = (u8 *) buf;
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int j, k;
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/* Separate the parity bits and the data bytes. */
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for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
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if ((i == 0) || (i == 8)) {
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int l;
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u8 msk;
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for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
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parity[k++] = buf8[i] & msk;
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i++;
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}
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else if (i == 16) {
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int l;
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u8 msk;
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for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
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parity[k++] = buf8[i] & msk;
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i++;
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for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
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parity[k++] = buf8[i] & msk;
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i++;
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}
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data[j++] = buf8[i];
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}
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err = -EIO;
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for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
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u8 hw8 = hweight8(data[i]);
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if ((hw8 & 0x1) && parity[i])
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goto out;
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else if (!(hw8 & 0x1) && !parity[i])
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goto out;
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}
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err = 0;
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goto out;
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}
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/* Bootstrap checksum at offset 0x10 */
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csum = calc_crc((unsigned char *) buf, 0x10);
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if(csum != cpu_to_le32(buf[0x10/4]))
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@ -8384,7 +8440,7 @@ static int tg3_test_link(struct tg3 *tp)
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/* Only test the commonly used registers */
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static int tg3_test_registers(struct tg3 *tp)
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{
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int i, is_5705;
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int i, is_5705, is_5750;
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u32 offset, read_mask, write_mask, val, save_val, read_val;
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static struct {
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u16 offset;
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@ -8392,6 +8448,7 @@ static int tg3_test_registers(struct tg3 *tp)
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#define TG3_FL_5705 0x1
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#define TG3_FL_NOT_5705 0x2
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#define TG3_FL_NOT_5788 0x4
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#define TG3_FL_NOT_5750 0x8
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u32 read_mask;
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u32 write_mask;
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} reg_tbl[] = {
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@ -8502,9 +8559,9 @@ static int tg3_test_registers(struct tg3 *tp)
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0xffffffff, 0x00000000 },
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/* Buffer Manager Control Registers. */
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{ BUFMGR_MB_POOL_ADDR, 0x0000,
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{ BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
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0x00000000, 0x007fff80 },
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{ BUFMGR_MB_POOL_SIZE, 0x0000,
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{ BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
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0x00000000, 0x007fffff },
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{ BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
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0x00000000, 0x0000003f },
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@ -8530,10 +8587,12 @@ static int tg3_test_registers(struct tg3 *tp)
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{ 0xffff, 0x0000, 0x00000000, 0x00000000 },
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};
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
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is_5705 = is_5750 = 0;
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
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is_5705 = 1;
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else
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is_5705 = 0;
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
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is_5750 = 1;
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}
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for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
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if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
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@ -8546,6 +8605,9 @@ static int tg3_test_registers(struct tg3 *tp)
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(reg_tbl[i].flags & TG3_FL_NOT_5788))
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continue;
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if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
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continue;
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offset = (u32) reg_tbl[i].offset;
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read_mask = reg_tbl[i].read_mask;
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write_mask = reg_tbl[i].write_mask;
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@ -8637,6 +8699,13 @@ static int tg3_test_memory(struct tg3 *tp)
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{ 0x00008000, 0x02000},
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{ 0x00010000, 0x0c000},
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{ 0xffffffff, 0x00000}
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}, mem_tbl_5906[] = {
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{ 0x00000200, 0x00008},
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{ 0x00004000, 0x00400},
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{ 0x00006000, 0x00400},
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{ 0x00008000, 0x01000},
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{ 0x00010000, 0x01000},
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{ 0xffffffff, 0x00000}
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};
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struct mem_entry *mem_tbl;
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int err = 0;
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@ -8646,6 +8715,8 @@ static int tg3_test_memory(struct tg3 *tp)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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mem_tbl = mem_tbl_5755;
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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mem_tbl = mem_tbl_5906;
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else
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mem_tbl = mem_tbl_5705;
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} else
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@ -8691,6 +8762,21 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
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} else if (loopback_mode == TG3_PHY_LOOPBACK) {
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u32 val;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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u32 phytest;
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if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
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u32 phy;
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tg3_writephy(tp, MII_TG3_EPHY_TEST,
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phytest | MII_TG3_EPHY_SHADOW_EN);
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if (!tg3_readphy(tp, 0x1b, &phy))
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tg3_writephy(tp, 0x1b, phy & ~0x20);
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if (!tg3_readphy(tp, 0x10, &phy))
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tg3_writephy(tp, 0x10, phy & ~0x4000);
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tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
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}
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}
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val = BMCR_LOOPBACK | BMCR_FULLDPLX;
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if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
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val |= BMCR_SPEED100;
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@ -8699,6 +8785,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
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tg3_writephy(tp, MII_BMCR, val);
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udelay(40);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
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/* reset to prevent losing 1st rx packet intermittently */
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if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
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tw32_f(MAC_RX_MODE, RX_MODE_RESET);
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@ -9112,7 +9201,9 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
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if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
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return;
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if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000))
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if ((magic != TG3_EEPROM_MAGIC) &&
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((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
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((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
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return;
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/*
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@ -1507,6 +1507,10 @@
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#define TG3_EEPROM_MAGIC 0x669955aa
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#define TG3_EEPROM_MAGIC_FW 0xa5000000
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#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
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#define TG3_EEPROM_MAGIC_HW 0xabcd
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#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
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/* 32K Window into NIC internal memory */
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#define NIC_SRAM_WIN_BASE 0x00008000
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