iio: ti_am335x_adc: Fix wrong samples received on 1st read
Previously we tried to read data form ADC even before ADC sequencer finished sampling. This led to wrong samples. We now wait on ADC status register idle bit to be set. Signed-off-by: Patil, Rachna <rachna@ti.com> Signed-off-by: Zubair Lutfullah <zubair.lutfullah@gmail.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
parent
a1a8e1dc11
commit
b1451e5468
2 changed files with 38 additions and 8 deletions
|
@ -60,7 +60,6 @@ static void tiadc_step_config(struct tiadc_device *adc_dev)
|
||||||
{
|
{
|
||||||
unsigned int stepconfig;
|
unsigned int stepconfig;
|
||||||
int i, steps;
|
int i, steps;
|
||||||
u32 step_en;
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* There are 16 configurable steps and 8 analog input
|
* There are 16 configurable steps and 8 analog input
|
||||||
|
@ -86,8 +85,7 @@ static void tiadc_step_config(struct tiadc_device *adc_dev)
|
||||||
adc_dev->channel_step[i] = steps;
|
adc_dev->channel_step[i] = steps;
|
||||||
steps++;
|
steps++;
|
||||||
}
|
}
|
||||||
step_en = get_adc_step_mask(adc_dev);
|
|
||||||
am335x_tsc_se_set(adc_dev->mfd_tscadc, step_en);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static const char * const chan_name_ain[] = {
|
static const char * const chan_name_ain[] = {
|
||||||
|
@ -142,10 +140,22 @@ static int tiadc_read_raw(struct iio_dev *indio_dev,
|
||||||
int *val, int *val2, long mask)
|
int *val, int *val2, long mask)
|
||||||
{
|
{
|
||||||
struct tiadc_device *adc_dev = iio_priv(indio_dev);
|
struct tiadc_device *adc_dev = iio_priv(indio_dev);
|
||||||
int i;
|
int i, map_val;
|
||||||
unsigned int fifo1count, read;
|
unsigned int fifo1count, read, stepid;
|
||||||
u32 step = UINT_MAX;
|
u32 step = UINT_MAX;
|
||||||
bool found = false;
|
bool found = false;
|
||||||
|
u32 step_en;
|
||||||
|
unsigned long timeout = jiffies + usecs_to_jiffies
|
||||||
|
(IDLE_TIMEOUT * adc_dev->channels);
|
||||||
|
step_en = get_adc_step_mask(adc_dev);
|
||||||
|
am335x_tsc_se_set(adc_dev->mfd_tscadc, step_en);
|
||||||
|
|
||||||
|
/* Wait for ADC sequencer to complete sampling */
|
||||||
|
while (tiadc_readl(adc_dev, REG_ADCFSM) & SEQ_STATUS) {
|
||||||
|
if (time_after(jiffies, timeout))
|
||||||
|
return -EAGAIN;
|
||||||
|
}
|
||||||
|
map_val = chan->channel + TOTAL_CHANNELS;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* When the sub-system is first enabled,
|
* When the sub-system is first enabled,
|
||||||
|
@ -170,12 +180,16 @@ static int tiadc_read_raw(struct iio_dev *indio_dev,
|
||||||
fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
|
fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT);
|
||||||
for (i = 0; i < fifo1count; i++) {
|
for (i = 0; i < fifo1count; i++) {
|
||||||
read = tiadc_readl(adc_dev, REG_FIFO1);
|
read = tiadc_readl(adc_dev, REG_FIFO1);
|
||||||
if (read >> 16 == step) {
|
stepid = read & FIFOREAD_CHNLID_MASK;
|
||||||
*val = read & 0xfff;
|
stepid = stepid >> 0x10;
|
||||||
|
|
||||||
|
if (stepid == map_val) {
|
||||||
|
read = read & FIFOREAD_DATA_MASK;
|
||||||
found = true;
|
found = true;
|
||||||
|
*val = read;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
am335x_tsc_se_update(adc_dev->mfd_tscadc);
|
|
||||||
if (found == false)
|
if (found == false)
|
||||||
return -EBUSY;
|
return -EBUSY;
|
||||||
return IIO_VAL_INT;
|
return IIO_VAL_INT;
|
||||||
|
|
|
@ -113,11 +113,27 @@
|
||||||
#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
|
#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
|
||||||
#define CNTRLREG_TSCENB BIT(7)
|
#define CNTRLREG_TSCENB BIT(7)
|
||||||
|
|
||||||
|
/* FIFO READ Register */
|
||||||
|
#define FIFOREAD_DATA_MASK (0xfff << 0)
|
||||||
|
#define FIFOREAD_CHNLID_MASK (0xf << 16)
|
||||||
|
|
||||||
|
/* Sequencer Status */
|
||||||
|
#define SEQ_STATUS BIT(5)
|
||||||
|
|
||||||
#define ADC_CLK 3000000
|
#define ADC_CLK 3000000
|
||||||
#define MAX_CLK_DIV 7
|
#define MAX_CLK_DIV 7
|
||||||
#define TOTAL_STEPS 16
|
#define TOTAL_STEPS 16
|
||||||
#define TOTAL_CHANNELS 8
|
#define TOTAL_CHANNELS 8
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ADC runs at 3MHz, and it takes
|
||||||
|
* 15 cycles to latch one data output.
|
||||||
|
* Hence the idle time for ADC to
|
||||||
|
* process one sample data would be
|
||||||
|
* around 5 micro seconds.
|
||||||
|
*/
|
||||||
|
#define IDLE_TIMEOUT 5 /* microsec */
|
||||||
|
|
||||||
#define TSCADC_CELLS 2
|
#define TSCADC_CELLS 2
|
||||||
|
|
||||||
struct ti_tscadc_dev {
|
struct ti_tscadc_dev {
|
||||||
|
|
Loading…
Reference in a new issue