x86: Simplify __HAVE_ARCH_CMPXCHG tests
Both the 32-bit and 64-bit cmpxchg.h header define __HAVE_ARCH_CMPXCHG and there's ifdeffery which checks it. But since both bitness define it, we can just as well move it up to the main cmpxchg header and simpify a bit of code in doing that. Signed-off-by: Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/20140711104338.GB17083@pd.tnic Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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6 changed files with 5 additions and 25 deletions
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@ -4,6 +4,8 @@
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#include <linux/compiler.h>
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#include <asm/alternative.h> /* Provides LOCK_PREFIX */
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#define __HAVE_ARCH_CMPXCHG 1
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/*
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* Non-existant functions to indicate usage errors at link time
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* (or compile-time if the compiler implements __compiletime_error().
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@ -143,7 +145,6 @@ extern void __add_wrong_size(void)
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# include <asm/cmpxchg_64.h>
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#endif
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#ifdef __HAVE_ARCH_CMPXCHG
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#define cmpxchg(ptr, old, new) \
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__cmpxchg(ptr, old, new, sizeof(*(ptr)))
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@ -152,7 +153,6 @@ extern void __add_wrong_size(void)
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#define cmpxchg_local(ptr, old, new) \
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__cmpxchg_local(ptr, old, new, sizeof(*(ptr)))
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#endif
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/*
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* xadd() adds "inc" to "*ptr" and atomically returns the previous
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@ -34,8 +34,6 @@ static inline void set_64bit(volatile u64 *ptr, u64 value)
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: "memory");
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}
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#define __HAVE_ARCH_CMPXCHG 1
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#ifdef CONFIG_X86_CMPXCHG64
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#define cmpxchg64(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
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@ -6,8 +6,6 @@ static inline void set_64bit(volatile u64 *ptr, u64 val)
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*ptr = val;
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}
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#define __HAVE_ARCH_CMPXCHG 1
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#define cmpxchg64(ptr, o, n) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
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@ -13,7 +13,7 @@
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#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
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#endif
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#if defined(CONFIG_X86_32) && defined(__HAVE_ARCH_CMPXCHG)
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#if defined(CONFIG_X86_32)
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/*
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* This lock provides nmi access to the CMOS/RTC registers. It has some
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* special properties. It is owned by a CPU and stores the index register
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@ -100,23 +100,11 @@ do { \
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static inline int __mutex_fastpath_trylock(atomic_t *count,
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int (*fail_fn)(atomic_t *))
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{
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/*
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* We have two variants here. The cmpxchg based one is the best one
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* because it never induce a false contention state. It is included
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* here because architectures using the inc/dec algorithms over the
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* xchg ones are much more likely to support cmpxchg natively.
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*
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* If not we fall back to the spinlock based variant - that is
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* just as efficient (and simpler) as a 'destructive' probing of
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* the mutex state would be.
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*/
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#ifdef __HAVE_ARCH_CMPXCHG
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/* cmpxchg because it never induces a false contention state. */
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if (likely(atomic_cmpxchg(count, 1, 0) == 1))
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return 1;
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return 0;
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#else
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return fail_fn(count);
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#endif
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}
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#endif /* _ASM_X86_MUTEX_32_H */
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@ -74,10 +74,6 @@ int acpi_fix_pin2_polarity __initdata;
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static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
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#endif
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#ifndef __HAVE_ARCH_CMPXCHG
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#warning ACPI uses CMPXCHG, i486 and later hardware
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#endif
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/* --------------------------------------------------------------------------
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Boot-time Configuration
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-------------------------------------------------------------------------- */
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