iwlwifi: rename restricted_mem to targ_mem
This patch renames restricted_mem suffix with more proper name targ_mem for function accessing memory on the nic in target mode Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
d860965200
commit
af7cca2a44
5 changed files with 54 additions and 56 deletions
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@ -96,7 +96,7 @@ const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
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* ... and set IWL_EVT_DISABLE to 1. */
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* ... and set IWL_EVT_DISABLE to 1. */
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void iwl_disable_events(struct iwl_priv *priv)
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void iwl_disable_events(struct iwl_priv *priv)
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{
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{
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int rc;
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int ret;
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int i;
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int i;
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u32 base; /* SRAM address of event log header */
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u32 base; /* SRAM address of event log header */
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u32 disable_ptr; /* SRAM address of event-disable bitmap array */
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u32 disable_ptr; /* SRAM address of event-disable bitmap array */
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@ -157,25 +157,24 @@ void iwl_disable_events(struct iwl_priv *priv)
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return;
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return;
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}
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}
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rc = iwl_grab_restricted_access(priv);
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ret = iwl_grab_restricted_access(priv);
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if (rc) {
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if (ret) {
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IWL_WARNING("Can not read from adapter at this time.\n");
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IWL_WARNING("Can not read from adapter at this time.\n");
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return;
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return;
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}
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}
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disable_ptr = iwl_read_restricted_mem(priv, base + (4 * sizeof(u32)));
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disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
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array_size = iwl_read_restricted_mem(priv, base + (5 * sizeof(u32)));
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array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
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iwl_release_restricted_access(priv);
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iwl_release_restricted_access(priv);
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if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
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if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
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IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
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IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
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disable_ptr);
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disable_ptr);
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rc = iwl_grab_restricted_access(priv);
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ret = iwl_grab_restricted_access(priv);
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for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
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for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
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iwl_write_restricted_mem(priv,
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iwl_write_targ_mem(priv,
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disable_ptr +
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disable_ptr + (i * sizeof(u32)),
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(i * sizeof(u32)),
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evt_disable[i]);
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evt_disable[i]);
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iwl_release_restricted_access(priv);
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iwl_release_restricted_access(priv);
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} else {
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} else {
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@ -1657,11 +1657,11 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
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priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
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priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
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a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
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a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
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for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
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for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
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iwl_write_restricted_mem(priv, a, 0);
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iwl_write_targ_mem(priv, a, 0);
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for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
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for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
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iwl_write_restricted_mem(priv, a, 0);
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iwl_write_targ_mem(priv, a, 0);
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for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
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for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
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iwl_write_restricted_mem(priv, a, 0);
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iwl_write_targ_mem(priv, a, 0);
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iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
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iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
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(priv->hw_setting.shared_phys +
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(priv->hw_setting.shared_phys +
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@ -1672,12 +1672,12 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
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for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
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for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
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iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
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iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
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iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
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iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
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iwl_write_restricted_mem(priv, priv->scd_base_addr +
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(i),
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SCD_CONTEXT_QUEUE_OFFSET(i),
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(SCD_WIN_SIZE <<
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(SCD_WIN_SIZE <<
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SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
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SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
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SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
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SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
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iwl_write_restricted_mem(priv, priv->scd_base_addr +
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(i) +
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SCD_CONTEXT_QUEUE_OFFSET(i) +
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sizeof(u32),
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sizeof(u32),
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(SCD_FRAME_LIMIT <<
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(SCD_FRAME_LIMIT <<
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@ -4156,14 +4156,14 @@ static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
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tbl_dw_addr = priv->scd_base_addr +
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tbl_dw_addr = priv->scd_base_addr +
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SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
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SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
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tbl_dw = iwl_read_restricted_mem(priv, tbl_dw_addr);
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tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
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if (txq_id & 0x1)
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if (txq_id & 0x1)
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tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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else
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else
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tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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iwl_write_restricted_mem(priv, tbl_dw_addr, tbl_dw);
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iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
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return 0;
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return 0;
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}
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}
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@ -4207,12 +4207,12 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
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/* supposes that ssn_idx is valid (!= 0xFFF) */
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/* supposes that ssn_idx is valid (!= 0xFFF) */
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iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
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iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
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iwl_write_restricted_mem(priv,
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iwl_write_targ_mem(priv,
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priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
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priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
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(SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
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(SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
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SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
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SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
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iwl_write_restricted_mem(priv, priv->scd_base_addr +
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iwl_write_targ_mem(priv, priv->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
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SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
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(SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
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(SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
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& SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
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& SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
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@ -411,21 +411,20 @@ static inline void iwl_clear_bits_prph(struct iwl_priv
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_iwl_write_prph(priv, reg, (val & ~mask));
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_iwl_write_prph(priv, reg, (val & ~mask));
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}
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}
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static inline u32 iwl_read_restricted_mem(struct iwl_priv *priv, u32 addr)
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static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
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{
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{
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iwl_write_restricted(priv, HBUS_TARG_MEM_RADDR, addr);
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iwl_write_restricted(priv, HBUS_TARG_MEM_RADDR, addr);
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return iwl_read_restricted(priv, HBUS_TARG_MEM_RDAT);
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return iwl_read_restricted(priv, HBUS_TARG_MEM_RDAT);
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}
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}
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static inline void iwl_write_restricted_mem(struct iwl_priv *priv, u32 addr,
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static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
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u32 val)
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{
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{
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iwl_write_restricted(priv, HBUS_TARG_MEM_WADDR, addr);
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iwl_write_restricted(priv, HBUS_TARG_MEM_WADDR, addr);
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iwl_write_restricted(priv, HBUS_TARG_MEM_WDAT, val);
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iwl_write_restricted(priv, HBUS_TARG_MEM_WDAT, val);
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}
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}
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static inline void iwl_write_restricted_mems(struct iwl_priv *priv, u32 addr,
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static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
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u32 len, u32 *values)
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u32 len, u32 *values)
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{
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{
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iwl_write_restricted(priv, HBUS_TARG_MEM_WADDR, addr);
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iwl_write_restricted(priv, HBUS_TARG_MEM_WADDR, addr);
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for (; 0 < len; len -= sizeof(u32), values++)
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for (; 0 < len; len -= sizeof(u32), values++)
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@ -4457,7 +4457,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
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return;
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return;
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}
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}
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count = iwl_read_restricted_mem(priv, base);
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count = iwl_read_targ_mem(priv, base);
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if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
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if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
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IWL_ERROR("Start IWL Error Log Dump:\n");
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IWL_ERROR("Start IWL Error Log Dump:\n");
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@ -4470,19 +4470,19 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
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for (i = ERROR_START_OFFSET;
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for (i = ERROR_START_OFFSET;
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i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
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i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
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i += ERROR_ELEM_SIZE) {
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i += ERROR_ELEM_SIZE) {
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desc = iwl_read_restricted_mem(priv, base + i);
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desc = iwl_read_targ_mem(priv, base + i);
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time =
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time =
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iwl_read_restricted_mem(priv, base + i + 1 * sizeof(u32));
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iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
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blink1 =
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blink1 =
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iwl_read_restricted_mem(priv, base + i + 2 * sizeof(u32));
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iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
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blink2 =
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blink2 =
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iwl_read_restricted_mem(priv, base + i + 3 * sizeof(u32));
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iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
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ilink1 =
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ilink1 =
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iwl_read_restricted_mem(priv, base + i + 4 * sizeof(u32));
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iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
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ilink2 =
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ilink2 =
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iwl_read_restricted_mem(priv, base + i + 5 * sizeof(u32));
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iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
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data1 =
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data1 =
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iwl_read_restricted_mem(priv, base + i + 6 * sizeof(u32));
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iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
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IWL_ERROR
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IWL_ERROR
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("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
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("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
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@ -4525,14 +4525,14 @@ static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
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/* "time" is actually "data" for mode 0 (no timestamp).
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/* "time" is actually "data" for mode 0 (no timestamp).
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* place event id # at far right for easier visual parsing. */
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* place event id # at far right for easier visual parsing. */
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for (i = 0; i < num_events; i++) {
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for (i = 0; i < num_events; i++) {
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ev = iwl_read_restricted_mem(priv, ptr);
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ev = iwl_read_targ_mem(priv, ptr);
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ptr += sizeof(u32);
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ptr += sizeof(u32);
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time = iwl_read_restricted_mem(priv, ptr);
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time = iwl_read_targ_mem(priv, ptr);
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ptr += sizeof(u32);
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ptr += sizeof(u32);
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if (mode == 0)
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if (mode == 0)
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IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
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IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
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else {
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else {
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data = iwl_read_restricted_mem(priv, ptr);
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data = iwl_read_targ_mem(priv, ptr);
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ptr += sizeof(u32);
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ptr += sizeof(u32);
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IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
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IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
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}
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}
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@ -4562,10 +4562,10 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
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}
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}
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/* event log header */
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/* event log header */
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capacity = iwl_read_restricted_mem(priv, base);
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capacity = iwl_read_targ_mem(priv, base);
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mode = iwl_read_restricted_mem(priv, base + (1 * sizeof(u32)));
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mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
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num_wraps = iwl_read_restricted_mem(priv, base + (2 * sizeof(u32)));
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num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
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next_entry = iwl_read_restricted_mem(priv, base + (3 * sizeof(u32)));
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next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
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size = num_wraps ? capacity : next_entry;
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size = num_wraps ? capacity : next_entry;
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@ -4785,7 +4785,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
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return;
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return;
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}
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}
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count = iwl_read_restricted_mem(priv, base);
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count = iwl_read_targ_mem(priv, base);
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if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
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if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
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IWL_ERROR("Start IWL Error Log Dump:\n");
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IWL_ERROR("Start IWL Error Log Dump:\n");
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@ -4793,15 +4793,15 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
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priv->status, priv->config, count);
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priv->status, priv->config, count);
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}
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}
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desc = iwl_read_restricted_mem(priv, base + 1 * sizeof(u32));
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desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
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blink1 = iwl_read_restricted_mem(priv, base + 3 * sizeof(u32));
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blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
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blink2 = iwl_read_restricted_mem(priv, base + 4 * sizeof(u32));
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blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
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ilink1 = iwl_read_restricted_mem(priv, base + 5 * sizeof(u32));
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ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
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ilink2 = iwl_read_restricted_mem(priv, base + 6 * sizeof(u32));
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ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
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data1 = iwl_read_restricted_mem(priv, base + 7 * sizeof(u32));
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data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
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data2 = iwl_read_restricted_mem(priv, base + 8 * sizeof(u32));
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data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
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line = iwl_read_restricted_mem(priv, base + 9 * sizeof(u32));
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line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
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time = iwl_read_restricted_mem(priv, base + 11 * sizeof(u32));
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time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
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IWL_ERROR("Desc Time "
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IWL_ERROR("Desc Time "
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"data1 data2 line\n");
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"data1 data2 line\n");
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@ -4845,14 +4845,14 @@ static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
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/* "time" is actually "data" for mode 0 (no timestamp).
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/* "time" is actually "data" for mode 0 (no timestamp).
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* place event id # at far right for easier visual parsing. */
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* place event id # at far right for easier visual parsing. */
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for (i = 0; i < num_events; i++) {
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for (i = 0; i < num_events; i++) {
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ev = iwl_read_restricted_mem(priv, ptr);
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ev = iwl_read_targ_mem(priv, ptr);
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ptr += sizeof(u32);
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ptr += sizeof(u32);
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time = iwl_read_restricted_mem(priv, ptr);
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time = iwl_read_targ_mem(priv, ptr);
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ptr += sizeof(u32);
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ptr += sizeof(u32);
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if (mode == 0)
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if (mode == 0)
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IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
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IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
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else {
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else {
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data = iwl_read_restricted_mem(priv, ptr);
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data = iwl_read_targ_mem(priv, ptr);
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ptr += sizeof(u32);
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ptr += sizeof(u32);
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||||||
IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
|
IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
|
||||||
}
|
}
|
||||||
|
@ -4882,10 +4882,10 @@ static void iwl_dump_nic_event_log(struct iwl_priv *priv)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* event log header */
|
/* event log header */
|
||||||
capacity = iwl_read_restricted_mem(priv, base);
|
capacity = iwl_read_targ_mem(priv, base);
|
||||||
mode = iwl_read_restricted_mem(priv, base + (1 * sizeof(u32)));
|
mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
|
||||||
num_wraps = iwl_read_restricted_mem(priv, base + (2 * sizeof(u32)));
|
num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
|
||||||
next_entry = iwl_read_restricted_mem(priv, base + (3 * sizeof(u32)));
|
next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
|
||||||
|
|
||||||
size = num_wraps ? capacity : next_entry;
|
size = num_wraps ? capacity : next_entry;
|
||||||
|
|
||||||
|
|
Loading…
Add table
Reference in a new issue