[TG3]: Add 5755 support
Add support for new chip 5755 which is very similar to 5787. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
b30bd282cb
commit
af36e6b6d7
3 changed files with 38 additions and 7 deletions
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@ -225,6 +225,10 @@ static struct pci_device_id tg3_pci_tbl[] = {
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
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@ -4557,6 +4561,7 @@ static int tg3_chip_reset(struct tg3 *tp)
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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tw32(GRC_FASTBOOT_PC, 0);
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@ -6152,6 +6157,9 @@ static int tg3_reset_hw(struct tg3 *tp)
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gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
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GRC_LCLCTRL_GPIO_OUTPUT3;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
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gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
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tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
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/* GPIO1 must be driven high for eeprom write protect */
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@ -6191,7 +6199,8 @@ static int tg3_reset_hw(struct tg3 *tp)
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}
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/* Enable host coalescing bug fix */
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
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val |= (1 << 29);
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tw32_f(WDMAC_MODE, val);
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@ -6249,6 +6258,9 @@ static int tg3_reset_hw(struct tg3 *tp)
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udelay(100);
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tp->rx_mode = RX_MODE_ENABLE;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
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tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
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tw32_f(MAC_RX_MODE, tp->rx_mode);
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udelay(10);
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@ -7907,7 +7919,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
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return 0;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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ethtool_op_set_tx_hw_csum(dev, data);
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else
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ethtool_op_set_tx_csum(dev, data);
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@ -8332,7 +8345,8 @@ static int tg3_test_memory(struct tg3 *tp)
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int i;
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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mem_tbl = mem_tbl_5755;
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else
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mem_tbl = mem_tbl_5705;
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@ -9310,6 +9324,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
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nvram_cmd |= NVRAM_CMD_LAST;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
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(tp->nvram_jedecnum == JEDEC_ST) &&
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(nvram_cmd & NVRAM_CMD_FIRST)) {
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@ -10044,6 +10059,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
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tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
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@ -10053,7 +10069,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
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tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
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} else
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@ -10063,6 +10080,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
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tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
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@ -10219,6 +10237,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
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tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
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/* Force the chip into D0. */
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err = tg3_set_power_state(tp, PCI_D0);
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if (err) {
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@ -10274,6 +10295,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
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if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787))
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tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
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@ -10413,7 +10435,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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/* All chips before 5787 can get confused if TX buffers
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* straddle the 4GB address boundary in some cases.
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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tp->dev->hard_start_xmit = tg3_start_xmit;
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else
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tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
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@ -11002,6 +11025,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
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case PHY_ID_BCM5752: return "5752";
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case PHY_ID_BCM5714: return "5714";
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case PHY_ID_BCM5780: return "5780";
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case PHY_ID_BCM5755: return "5755";
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case PHY_ID_BCM5787: return "5787";
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case PHY_ID_BCM8002: return "8002/serdes";
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case 0: return "serdes";
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@ -11350,7 +11374,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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* checksumming.
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*/
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if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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dev->features |= NETIF_F_HW_CSUM;
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else
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dev->features |= NETIF_F_IP_CSUM;
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@ -138,6 +138,7 @@
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#define ASIC_REV_5752 0x06
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#define ASIC_REV_5780 0x08
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#define ASIC_REV_5714 0x09
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#define ASIC_REV_5755 0x0a
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#define ASIC_REV_5787 0x0b
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#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
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#define CHIPREV_5700_AX 0x70
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@ -456,6 +457,7 @@
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#define RX_MODE_PROMISC 0x00000100
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#define RX_MODE_NO_CRC_CHECK 0x00000200
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#define RX_MODE_KEEP_VLAN_TAG 0x00000400
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#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
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#define MAC_RX_STATUS 0x0000046c
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#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
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#define RX_STATUS_XOFF_RCVD 0x00000002
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@ -1340,6 +1342,7 @@
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#define GRC_LCLCTRL_CLEARINT 0x00000002
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#define GRC_LCLCTRL_SETINT 0x00000004
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#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
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#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
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#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
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#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
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#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
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@ -2259,6 +2262,7 @@ struct tg3 {
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#define PHY_ID_BCM5752 0x60008100
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#define PHY_ID_BCM5714 0x60008340
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#define PHY_ID_BCM5780 0x60008350
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#define PHY_ID_BCM5755 0xbc050cc0
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#define PHY_ID_BCM5787 0xbc050ce0
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#define PHY_ID_BCM8002 0x60010140
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#define PHY_ID_INVALID 0xffffffff
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@ -2286,7 +2290,7 @@ struct tg3 {
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(X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
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(X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
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(X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
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(X) == PHY_ID_BCM8002)
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(X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM8002)
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struct tg3_hw_stats *hw_stats;
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dma_addr_t stats_mapping;
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@ -1864,11 +1864,13 @@
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#define PCI_DEVICE_ID_TIGON3_5780S 0x166b
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#define PCI_DEVICE_ID_TIGON3_5705F 0x166e
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#define PCI_DEVICE_ID_TIGON3_5754M 0x1672
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#define PCI_DEVICE_ID_TIGON3_5755M 0x1673
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#define PCI_DEVICE_ID_TIGON3_5750 0x1676
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#define PCI_DEVICE_ID_TIGON3_5751 0x1677
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#define PCI_DEVICE_ID_TIGON3_5715 0x1678
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#define PCI_DEVICE_ID_TIGON3_5715S 0x1679
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#define PCI_DEVICE_ID_TIGON3_5754 0x167a
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#define PCI_DEVICE_ID_TIGON3_5755 0x167b
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#define PCI_DEVICE_ID_TIGON3_5750M 0x167c
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#define PCI_DEVICE_ID_TIGON3_5751M 0x167d
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#define PCI_DEVICE_ID_TIGON3_5751F 0x167e
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