ARM: zynq: PM: Enable A9 internal clock gating feature
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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3 changed files with 30 additions and 0 deletions
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@ -98,6 +98,11 @@ static int __init zynq_get_revision(void)
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return revision;
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}
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static void __init zynq_init_late(void)
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{
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zynq_core_pm_init();
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}
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/**
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* zynq_init_machine - System specific initialization, intended to be
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* called from board specific initialization.
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@ -204,6 +209,7 @@ DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
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.map_io = zynq_map_io,
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.init_irq = zynq_irq_init,
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.init_machine = zynq_init_machine,
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.init_late = zynq_init_late,
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.init_time = zynq_timer_init,
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.dt_compat = zynq_dt_match,
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.reserve = zynq_memory_init,
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@ -40,4 +40,15 @@ extern void __iomem *zynq_scu_base;
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/* Hotplug */
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extern void zynq_platform_cpu_die(unsigned int cpu);
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static inline void zynq_core_pm_init(void)
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{
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/* A9 clock gating */
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asm volatile ("mrc p15, 0, r12, c15, c0, 0\n"
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"orr r12, r12, #1\n"
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"mcr p15, 0, r12, c15, c0, 0\n"
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: /* no outputs */
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: /* no inputs */
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: "r12");
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}
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#endif
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@ -112,6 +112,18 @@ static void __init zynq_smp_prepare_cpus(unsigned int max_cpus)
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scu_enable(zynq_scu_base);
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}
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/**
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* zynq_secondary_init - Initialize secondary CPU cores
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* @cpu: CPU that is initialized
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*
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* This function is in the hotplug path. Don't move it into the
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* init section!!
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*/
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static void zynq_secondary_init(unsigned int cpu)
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{
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zynq_core_pm_init();
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int zynq_cpu_kill(unsigned cpu)
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{
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@ -124,6 +136,7 @@ struct smp_operations zynq_smp_ops __initdata = {
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.smp_init_cpus = zynq_smp_init_cpus,
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.smp_prepare_cpus = zynq_smp_prepare_cpus,
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.smp_boot_secondary = zynq_boot_secondary,
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.smp_secondary_init = zynq_secondary_init,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = zynq_platform_cpu_die,
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.cpu_kill = zynq_cpu_kill,
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