amd64_edac: Sanitize syndrome extraction
Remove the two syndrome extraction macros and add a single function which does the same thing but with proper typechecking. While at it, make sure to cache ECC syndrome size and dump it in debug output. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
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9fe6206f40
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ad6a32e969
2 changed files with 54 additions and 32 deletions
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@ -796,6 +796,11 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
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static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
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static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
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static u16 extract_syndrome(struct err_regs *err)
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{
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return ((err->nbsh >> 15) & 0xff) | ((err->nbsl >> 16) & 0xff00);
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}
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static void amd64_cpu_display_info(struct amd64_pvt *pvt)
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static void amd64_cpu_display_info(struct amd64_pvt *pvt)
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{
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{
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if (boot_cpu_data.x86 == 0x11)
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if (boot_cpu_data.x86 == 0x11)
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@ -888,6 +893,9 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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return;
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return;
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}
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}
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amd64_printk(KERN_INFO, "using %s syndromes.\n",
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((pvt->syn_type == 8) ? "x8" : "x4"));
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/* Only if NOT ganged does dclr1 have valid info */
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/* Only if NOT ganged does dclr1 have valid info */
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if (!dct_ganging_enabled(pvt))
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if (!dct_ganging_enabled(pvt))
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amd64_dump_dramcfg_low(pvt->dclr1, 1);
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amd64_dump_dramcfg_low(pvt->dclr1, 1);
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@ -1101,20 +1109,17 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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}
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}
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static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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struct err_regs *info,
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struct err_regs *err_info, u64 sys_addr)
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u64 sys_addr)
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{
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{
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struct mem_ctl_info *src_mci;
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struct mem_ctl_info *src_mci;
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unsigned short syndrome;
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int channel, csrow;
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int channel, csrow;
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u32 page, offset;
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u32 page, offset;
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u16 syndrome;
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/* Extract the syndrome parts and form a 16-bit syndrome */
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syndrome = extract_syndrome(err_info);
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syndrome = HIGH_SYNDROME(info->nbsl) << 8;
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syndrome |= LOW_SYNDROME(info->nbsh);
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/* CHIPKILL enabled */
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/* CHIPKILL enabled */
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if (info->nbcfg & K8_NBCFG_CHIPKILL) {
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if (err_info->nbcfg & K8_NBCFG_CHIPKILL) {
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channel = get_channel_from_ecc_syndrome(mci, syndrome);
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channel = get_channel_from_ecc_syndrome(mci, syndrome);
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if (channel < 0) {
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if (channel < 0) {
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/*
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/*
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@ -1123,8 +1128,8 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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* as suspect.
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* as suspect.
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*/
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*/
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amd64_mc_printk(mci, KERN_WARNING,
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amd64_mc_printk(mci, KERN_WARNING,
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"unknown syndrome 0x%x - possible error "
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"unknown syndrome 0x%04x - possible "
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"reporting race\n", syndrome);
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"error reporting race\n", syndrome);
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edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
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edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
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return;
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return;
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}
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}
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@ -1654,13 +1659,13 @@ static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
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* (MCX_ADDR).
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* (MCX_ADDR).
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*/
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*/
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static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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struct err_regs *info,
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struct err_regs *err_info,
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u64 sys_addr)
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u64 sys_addr)
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{
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 page, offset;
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u32 page, offset;
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unsigned short syndrome;
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int nid, csrow, chan = 0;
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int nid, csrow, chan = 0;
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u16 syndrome;
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csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
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csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
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@ -1671,8 +1676,7 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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error_address_to_page_and_offset(sys_addr, &page, &offset);
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error_address_to_page_and_offset(sys_addr, &page, &offset);
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syndrome = HIGH_SYNDROME(info->nbsl) << 8;
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syndrome = extract_syndrome(err_info);
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syndrome |= LOW_SYNDROME(info->nbsh);
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/*
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/*
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* We need the syndromes for channel detection only when we're
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* We need the syndromes for channel detection only when we're
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@ -1878,7 +1882,7 @@ static u16 x8_vectors[] = {
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};
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};
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static int decode_syndrome(u16 syndrome, u16 *vectors, int num_vecs,
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static int decode_syndrome(u16 syndrome, u16 *vectors, int num_vecs,
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int v_dim)
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int v_dim)
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{
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{
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unsigned int i, err_sym;
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unsigned int i, err_sym;
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@ -1955,23 +1959,23 @@ static int map_err_sym_to_channel(int err_sym, int sym_size)
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static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
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static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
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{
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 value = 0;
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int err_sym = -1;
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int err_sym = 0;
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if (boot_cpu_data.x86 == 0x10) {
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if (pvt->syn_type == 8)
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err_sym = decode_syndrome(syndrome, x8_vectors,
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amd64_read_pci_cfg(pvt->misc_f3_ctl, 0x180, &value);
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ARRAY_SIZE(x8_vectors),
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pvt->syn_type);
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/* F3x180[EccSymbolSize]=1 => x8 symbols */
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else if (pvt->syn_type == 4)
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if (boot_cpu_data.x86_model > 7 &&
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err_sym = decode_syndrome(syndrome, x4_vectors,
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value & BIT(25)) {
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ARRAY_SIZE(x4_vectors),
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err_sym = decode_syndrome(syndrome, x8_vectors,
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pvt->syn_type);
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ARRAY_SIZE(x8_vectors), 8);
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else {
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return map_err_sym_to_channel(err_sym, 8);
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amd64_printk(KERN_WARNING, "%s: Illegal syndrome type: %u\n",
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}
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__func__, pvt->syn_type);
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return err_sym;
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}
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}
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err_sym = decode_syndrome(syndrome, x4_vectors, ARRAY_SIZE(x4_vectors), 4);
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return map_err_sym_to_channel(err_sym, 4);
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return map_err_sym_to_channel(err_sym, pvt->syn_type);
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}
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}
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/*
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/*
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@ -2284,6 +2288,7 @@ static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt)
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static void amd64_read_mc_registers(struct amd64_pvt *pvt)
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static void amd64_read_mc_registers(struct amd64_pvt *pvt)
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{
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{
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u64 msr_val;
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u64 msr_val;
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u32 tmp;
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int dram;
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int dram;
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/*
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/*
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@ -2349,10 +2354,22 @@ static void amd64_read_mc_registers(struct amd64_pvt *pvt)
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amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
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amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
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amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0);
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amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0);
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if (!dct_ganging_enabled(pvt) && boot_cpu_data.x86 >= 0x10) {
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if (boot_cpu_data.x86 >= 0x10) {
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amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1);
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if (!dct_ganging_enabled(pvt)) {
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amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_1, &pvt->dchr1);
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amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1);
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amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_1, &pvt->dchr1);
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}
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amd64_read_pci_cfg(pvt->misc_f3_ctl, EXT_NB_MCA_CFG, &tmp);
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}
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}
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if (boot_cpu_data.x86 == 0x10 &&
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boot_cpu_data.x86_model > 7 &&
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/* F3x180[EccSymbolSize]=1 => x8 symbols */
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tmp & BIT(25))
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pvt->syn_type = 8;
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else
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pvt->syn_type = 4;
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amd64_dump_misc_regs(pvt);
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amd64_dump_misc_regs(pvt);
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}
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}
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@ -382,6 +382,8 @@ enum {
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#define K8_NBCAP_SECDED BIT(3)
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#define K8_NBCAP_SECDED BIT(3)
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#define K8_NBCAP_DCT_DUAL BIT(0)
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#define K8_NBCAP_DCT_DUAL BIT(0)
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#define EXT_NB_MCA_CFG 0x180
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/* MSRs */
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/* MSRs */
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#define K8_MSR_MCGCTL_NBE BIT(4)
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#define K8_MSR_MCGCTL_NBE BIT(4)
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@ -471,6 +473,9 @@ struct amd64_pvt {
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u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */
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u32 dram_ctl_select_high; /* DRAM Controller Select High Reg */
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u32 online_spare; /* On-Line spare Reg */
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u32 online_spare; /* On-Line spare Reg */
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/* x4 or x8 syndromes in use */
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u8 syn_type;
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/* temp storage for when input is received from sysfs */
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/* temp storage for when input is received from sysfs */
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struct err_regs ctl_error_info;
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struct err_regs ctl_error_info;
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