drm/i915: Disable RC6 on Ironlake
The automatic powersaving feature is once again causing havoc, with 100% reliable hangs on boot and resume on affected machines. Reported-by: Francesco Allertsen <fallertsen@gmail.com> Reported-by: Gui Rui <chaos.proton@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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72389a33b8
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4 changed files with 57 additions and 46 deletions
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@ -46,6 +46,9 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
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unsigned int i915_powersave = 1;
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module_param_named(powersave, i915_powersave, int, 0600);
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unsigned int i915_enable_rc6 = 0;
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module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
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unsigned int i915_lvds_downclock = 0;
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module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
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@ -360,7 +363,7 @@ static int i915_drm_thaw(struct drm_device *dev)
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/* Resume the modeset for every activated CRTC */
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drm_helper_resume_force_mode(dev);
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if (dev_priv->renderctx && dev_priv->pwrctx)
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if (IS_IRONLAKE_M(dev))
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ironlake_enable_rc6(dev);
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}
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@ -958,6 +958,7 @@ extern unsigned int i915_fbpercrtc;
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extern unsigned int i915_powersave;
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extern unsigned int i915_lvds_downclock;
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extern unsigned int i915_panel_use_ssc;
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extern unsigned int i915_enable_rc6;
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extern int i915_suspend(struct drm_device *dev, pm_message_t state);
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extern int i915_resume(struct drm_device *dev);
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@ -6463,29 +6463,19 @@ void intel_enable_clock_gating(struct drm_device *dev)
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}
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}
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void intel_disable_clock_gating(struct drm_device *dev)
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static void ironlake_teardown_rc6(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->renderctx) {
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struct drm_i915_gem_object *obj = dev_priv->renderctx;
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I915_WRITE(CCID, 0);
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POSTING_READ(CCID);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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i915_gem_object_unpin(dev_priv->renderctx);
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drm_gem_object_unreference(&dev_priv->renderctx->base);
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dev_priv->renderctx = NULL;
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}
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if (dev_priv->pwrctx) {
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struct drm_i915_gem_object *obj = dev_priv->pwrctx;
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I915_WRITE(PWRCTXA, 0);
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POSTING_READ(PWRCTXA);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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i915_gem_object_unpin(dev_priv->pwrctx);
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drm_gem_object_unreference(&dev_priv->pwrctx->base);
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dev_priv->pwrctx = NULL;
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}
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}
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@ -6494,21 +6484,39 @@ static void ironlake_disable_rc6(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (I915_READ(PWRCTXA)) {
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/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
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I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
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wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
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10);
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POSTING_READ(CCID);
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50);
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I915_WRITE(PWRCTXA, 0);
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POSTING_READ(PWRCTXA);
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I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
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POSTING_READ(RSTDBYCTL);
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i915_gem_object_unpin(dev_priv->renderctx);
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drm_gem_object_unreference(&dev_priv->renderctx->base);
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dev_priv->renderctx = NULL;
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i915_gem_object_unpin(dev_priv->pwrctx);
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drm_gem_object_unreference(&dev_priv->pwrctx->base);
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dev_priv->pwrctx = NULL;
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}
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ironlake_disable_rc6(dev);
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}
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static int ironlake_setup_rc6(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->renderctx == NULL)
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dev_priv->renderctx = intel_alloc_context_page(dev);
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if (!dev_priv->renderctx)
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return -ENOMEM;
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if (dev_priv->pwrctx == NULL)
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dev_priv->pwrctx = intel_alloc_context_page(dev);
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if (!dev_priv->pwrctx) {
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ironlake_teardown_rc6(dev);
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return -ENOMEM;
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}
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return 0;
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}
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void ironlake_enable_rc6(struct drm_device *dev)
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@ -6516,15 +6524,26 @@ void ironlake_enable_rc6(struct drm_device *dev)
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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/* rc6 disabled by default due to repeated reports of hanging during
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* boot and resume.
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*/
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if (!i915_enable_rc6)
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return;
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ret = ironlake_setup_rc6(dev);
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if (ret)
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return;
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/*
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* GPU can automatically power down the render unit if given a page
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* to save state.
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*/
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ret = BEGIN_LP_RING(6);
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if (ret) {
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ironlake_disable_rc6(dev);
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ironlake_teardown_rc6(dev);
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return;
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}
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OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
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OUT_RING(MI_SET_CONTEXT);
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OUT_RING(dev_priv->renderctx->gtt_offset |
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@ -6541,6 +6560,7 @@ void ironlake_enable_rc6(struct drm_device *dev)
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I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
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}
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/* Set up chip specific display functions */
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static void intel_init_display(struct drm_device *dev)
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{
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@ -6783,21 +6803,9 @@ void intel_modeset_init(struct drm_device *dev)
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if (IS_GEN6(dev))
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gen6_enable_rps(dev_priv);
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if (IS_IRONLAKE_M(dev)) {
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dev_priv->renderctx = intel_alloc_context_page(dev);
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if (!dev_priv->renderctx)
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goto skip_rc6;
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dev_priv->pwrctx = intel_alloc_context_page(dev);
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if (!dev_priv->pwrctx) {
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i915_gem_object_unpin(dev_priv->renderctx);
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drm_gem_object_unreference(&dev_priv->renderctx->base);
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dev_priv->renderctx = NULL;
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goto skip_rc6;
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}
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if (IS_IRONLAKE_M(dev))
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ironlake_enable_rc6(dev);
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}
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skip_rc6:
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INIT_WORK(&dev_priv->idle_work, intel_idle_update);
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setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
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(unsigned long)dev);
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@ -298,7 +298,6 @@ extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
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extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
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u16 *blue, int regno);
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extern void intel_enable_clock_gating(struct drm_device *dev);
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extern void intel_disable_clock_gating(struct drm_device *dev);
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extern void ironlake_enable_drps(struct drm_device *dev);
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extern void ironlake_disable_drps(struct drm_device *dev);
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extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
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