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drm/i915: Disable RC6 on Ironlake

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The automatic powersaving feature is once again causing havoc, with 100%
reliable hangs on boot and resume on affected machines.

Reported-by: Francesco Allertsen <fallertsen@gmail.com>
Reported-by: Gui Rui <chaos.proton@gmail.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2011-02-09 16:15:32 +00:00
parent 72389a33b8
commit ac66808814
4 changed files with 57 additions and 46 deletions
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5
drivers/gpu/drm/i915/i915_drv.c
View file

@ -46,6 +46,9 @@ module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
unsigned int i915_powersave = 1; unsigned int i915_powersave = 1;
module_param_named(powersave, i915_powersave, int, 0600); module_param_named(powersave, i915_powersave, int, 0600);
unsigned int i915_enable_rc6 = 0;
module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
unsigned int i915_lvds_downclock = 0; unsigned int i915_lvds_downclock = 0;
module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
@ -360,7 +363,7 @@ static int i915_drm_thaw(struct drm_device *dev)
/* Resume the modeset for every activated CRTC */ /* Resume the modeset for every activated CRTC */
drm_helper_resume_force_mode(dev); drm_helper_resume_force_mode(dev);
if (dev_priv->renderctx && dev_priv->pwrctx) if (IS_IRONLAKE_M(dev))
ironlake_enable_rc6(dev); ironlake_enable_rc6(dev);
} }

1
drivers/gpu/drm/i915/i915_drv.h
View file

@ -958,6 +958,7 @@ extern unsigned int i915_fbpercrtc;
extern unsigned int i915_powersave; extern unsigned int i915_powersave;
extern unsigned int i915_lvds_downclock; extern unsigned int i915_lvds_downclock;
extern unsigned int i915_panel_use_ssc; extern unsigned int i915_panel_use_ssc;
extern unsigned int i915_enable_rc6;
extern int i915_suspend(struct drm_device *dev, pm_message_t state); extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev); extern int i915_resume(struct drm_device *dev);

96
drivers/gpu/drm/i915/intel_display.c
View file

@ -6463,29 +6463,19 @@ void intel_enable_clock_gating(struct drm_device *dev)
} }
} }
void intel_disable_clock_gating(struct drm_device *dev) static void ironlake_teardown_rc6(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
if (dev_priv->renderctx) { if (dev_priv->renderctx) {
struct drm_i915_gem_object *obj = dev_priv->renderctx; i915_gem_object_unpin(dev_priv->renderctx);
drm_gem_object_unreference(&dev_priv->renderctx->base);
I915_WRITE(CCID, 0);
POSTING_READ(CCID);
i915_gem_object_unpin(obj);
drm_gem_object_unreference(&obj->base);
dev_priv->renderctx = NULL; dev_priv->renderctx = NULL;
} }
if (dev_priv->pwrctx) { if (dev_priv->pwrctx) {
struct drm_i915_gem_object *obj = dev_priv->pwrctx; i915_gem_object_unpin(dev_priv->pwrctx);
drm_gem_object_unreference(&dev_priv->pwrctx->base);
I915_WRITE(PWRCTXA, 0);
POSTING_READ(PWRCTXA);
i915_gem_object_unpin(obj);
drm_gem_object_unreference(&obj->base);
dev_priv->pwrctx = NULL; dev_priv->pwrctx = NULL;
} }
} }
@ -6494,21 +6484,39 @@ static void ironlake_disable_rc6(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ if (I915_READ(PWRCTXA)) {
I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
10); wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
POSTING_READ(CCID); 50);
I915_WRITE(PWRCTXA, 0);
POSTING_READ(PWRCTXA); I915_WRITE(PWRCTXA, 0);
I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); POSTING_READ(PWRCTXA);
POSTING_READ(RSTDBYCTL);
i915_gem_object_unpin(dev_priv->renderctx); I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
drm_gem_object_unreference(&dev_priv->renderctx->base); POSTING_READ(RSTDBYCTL);
dev_priv->renderctx = NULL; }
i915_gem_object_unpin(dev_priv->pwrctx);
drm_gem_object_unreference(&dev_priv->pwrctx->base); ironlake_disable_rc6(dev);
dev_priv->pwrctx = NULL; }
static int ironlake_setup_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
if (dev_priv->renderctx == NULL)
dev_priv->renderctx = intel_alloc_context_page(dev);
if (!dev_priv->renderctx)
return -ENOMEM;
if (dev_priv->pwrctx == NULL)
dev_priv->pwrctx = intel_alloc_context_page(dev);
if (!dev_priv->pwrctx) {
ironlake_teardown_rc6(dev);
return -ENOMEM;
}
return 0;
} }
void ironlake_enable_rc6(struct drm_device *dev) void ironlake_enable_rc6(struct drm_device *dev)
@ -6516,15 +6524,26 @@ void ironlake_enable_rc6(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int ret; int ret;
/* rc6 disabled by default due to repeated reports of hanging during
* boot and resume.
*/
if (!i915_enable_rc6)
return;
ret = ironlake_setup_rc6(dev);
if (ret)
return;
/* /*
* GPU can automatically power down the render unit if given a page * GPU can automatically power down the render unit if given a page
* to save state. * to save state.
*/ */
ret = BEGIN_LP_RING(6); ret = BEGIN_LP_RING(6);
if (ret) { if (ret) {
ironlake_disable_rc6(dev); ironlake_teardown_rc6(dev);
return; return;
} }
OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
OUT_RING(MI_SET_CONTEXT); OUT_RING(MI_SET_CONTEXT);
OUT_RING(dev_priv->renderctx->gtt_offset | OUT_RING(dev_priv->renderctx->gtt_offset |
@ -6541,6 +6560,7 @@ void ironlake_enable_rc6(struct drm_device *dev)
I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
} }
/* Set up chip specific display functions */ /* Set up chip specific display functions */
static void intel_init_display(struct drm_device *dev) static void intel_init_display(struct drm_device *dev)
{ {
@ -6783,21 +6803,9 @@ void intel_modeset_init(struct drm_device *dev)
if (IS_GEN6(dev)) if (IS_GEN6(dev))
gen6_enable_rps(dev_priv); gen6_enable_rps(dev_priv);
if (IS_IRONLAKE_M(dev)) { if (IS_IRONLAKE_M(dev))
dev_priv->renderctx = intel_alloc_context_page(dev);
if (!dev_priv->renderctx)
goto skip_rc6;
dev_priv->pwrctx = intel_alloc_context_page(dev);
if (!dev_priv->pwrctx) {
i915_gem_object_unpin(dev_priv->renderctx);
drm_gem_object_unreference(&dev_priv->renderctx->base);
dev_priv->renderctx = NULL;
goto skip_rc6;
}
ironlake_enable_rc6(dev); ironlake_enable_rc6(dev);
}
skip_rc6:
INIT_WORK(&dev_priv->idle_work, intel_idle_update); INIT_WORK(&dev_priv->idle_work, intel_idle_update);
setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
(unsigned long)dev); (unsigned long)dev);

1
drivers/gpu/drm/i915/intel_drv.h
View file

@ -298,7 +298,6 @@ extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
u16 *blue, int regno); u16 *blue, int regno);
extern void intel_enable_clock_gating(struct drm_device *dev); extern void intel_enable_clock_gating(struct drm_device *dev);
extern void intel_disable_clock_gating(struct drm_device *dev);
extern void ironlake_enable_drps(struct drm_device *dev); extern void ironlake_enable_drps(struct drm_device *dev);
extern void ironlake_disable_drps(struct drm_device *dev); extern void ironlake_disable_drps(struct drm_device *dev);
extern void gen6_enable_rps(struct drm_i915_private *dev_priv); extern void gen6_enable_rps(struct drm_i915_private *dev_priv);