[media] marvell-cam: Separate out the Marvell camera core
There will eventually be multiple users of the core camera controller, so separate it from the bus/platform/i2c stuff. I've tried to do the minimal set of changes to get the driver functioning in this configuration; I did clean up a bunch of old checkpatch gripes in the process. This driver works like the old one did on OLPC XO 1 systems. Cc: Daniel Drake <dsd@laptop.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Jonathan Corbet
Mauro Carvalho Chehab
parent
f8fc729870
commit
abfa3df36c
6 changed files with 2571 additions and 2433 deletions
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@ -1 +1,2 @@
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obj-$(CONFIG_VIDEO_CAFE_CCIC) += cafe_ccic.o
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cafe_ccic-y := cafe-driver.o mcam-core.o
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570
drivers/media/video/marvell-ccic/cafe-driver.c
Normal file
570
drivers/media/video/marvell-ccic/cafe-driver.c
Normal file
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@ -0,0 +1,570 @@
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/*
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* A driver for the CMOS camera controller in the Marvell 88ALP01 "cafe"
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* multifunction chip. Currently works with the Omnivision OV7670
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* sensor.
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*
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* The data sheet for this device can be found at:
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* http://www.marvell.com/products/pc_connectivity/88alp01/
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*
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* Copyright 2006-11 One Laptop Per Child Association, Inc.
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* Copyright 2006-11 Jonathan Corbet <corbet@lwn.net>
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*
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* Written by Jonathan Corbet, corbet@lwn.net.
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*
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* v4l2_device/v4l2_subdev conversion by:
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* Copyright (C) 2009 Hans Verkuil <hverkuil@xs4all.nl>
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*
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* Note: this conversion is untested! Please contact the linux-media
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* mailinglist if you can test this, together with the test results.
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*
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* This file may be distributed under the terms of the GNU General
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* Public License, version 2.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/videodev2.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-chip-ident.h>
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#include <linux/device.h>
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#include <linux/wait.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "mcam-core.h"
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#define CAFE_VERSION 0x000002
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/*
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* Parameters.
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*/
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MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
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MODULE_DESCRIPTION("Marvell 88ALP01 CMOS Camera Controller driver");
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MODULE_LICENSE("GPL");
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MODULE_SUPPORTED_DEVICE("Video");
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struct cafe_camera {
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int registered; /* Fully initialized? */
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struct mcam_camera mcam;
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struct pci_dev *pdev;
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wait_queue_head_t smbus_wait; /* Waiting on i2c events */
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};
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/*
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* Debugging and related.
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*/
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#define cam_err(cam, fmt, arg...) \
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dev_err(&(cam)->pdev->dev, fmt, ##arg);
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#define cam_warn(cam, fmt, arg...) \
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dev_warn(&(cam)->pdev->dev, fmt, ##arg);
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/* -------------------------------------------------------------------- */
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/*
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* The I2C/SMBUS interface to the camera itself starts here. The
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* controller handles SMBUS itself, presenting a relatively simple register
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* interface; all we have to do is to tell it where to route the data.
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*/
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#define CAFE_SMBUS_TIMEOUT (HZ) /* generous */
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static inline struct cafe_camera *to_cam(struct v4l2_device *dev)
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{
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struct mcam_camera *m = container_of(dev, struct mcam_camera, v4l2_dev);
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return container_of(m, struct cafe_camera, mcam);
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}
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static int cafe_smbus_write_done(struct mcam_camera *mcam)
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{
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unsigned long flags;
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int c1;
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/*
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* We must delay after the interrupt, or the controller gets confused
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* and never does give us good status. Fortunately, we don't do this
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* often.
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*/
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udelay(20);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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c1 = mcam_reg_read(mcam, REG_TWSIC1);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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return (c1 & (TWSIC1_WSTAT|TWSIC1_ERROR)) != TWSIC1_WSTAT;
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}
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static int cafe_smbus_write_data(struct cafe_camera *cam,
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u16 addr, u8 command, u8 value)
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{
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unsigned int rval;
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unsigned long flags;
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struct mcam_camera *mcam = &cam->mcam;
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spin_lock_irqsave(&mcam->dev_lock, flags);
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rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
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rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
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/*
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* Marvell sez set clkdiv to all 1's for now.
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*/
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rval |= TWSIC0_CLKDIV;
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mcam_reg_write(mcam, REG_TWSIC0, rval);
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(void) mcam_reg_read(mcam, REG_TWSIC1); /* force write */
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rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
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mcam_reg_write(mcam, REG_TWSIC1, rval);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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/* Unfortunately, reading TWSIC1 too soon after sending a command
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* causes the device to die.
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* Use a busy-wait because we often send a large quantity of small
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* commands at-once; using msleep() would cause a lot of context
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* switches which take longer than 2ms, resulting in a noticeable
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* boot-time and capture-start delays.
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*/
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mdelay(2);
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/*
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* Another sad fact is that sometimes, commands silently complete but
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* cafe_smbus_write_done() never becomes aware of this.
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* This happens at random and appears to possible occur with any
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* command.
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* We don't understand why this is. We work around this issue
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* with the timeout in the wait below, assuming that all commands
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* complete within the timeout.
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*/
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wait_event_timeout(cam->smbus_wait, cafe_smbus_write_done(mcam),
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CAFE_SMBUS_TIMEOUT);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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rval = mcam_reg_read(mcam, REG_TWSIC1);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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if (rval & TWSIC1_WSTAT) {
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cam_err(cam, "SMBUS write (%02x/%02x/%02x) timed out\n", addr,
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command, value);
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return -EIO;
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}
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if (rval & TWSIC1_ERROR) {
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cam_err(cam, "SMBUS write (%02x/%02x/%02x) error\n", addr,
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command, value);
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return -EIO;
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}
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return 0;
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}
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static int cafe_smbus_read_done(struct mcam_camera *mcam)
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{
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unsigned long flags;
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int c1;
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/*
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* We must delay after the interrupt, or the controller gets confused
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* and never does give us good status. Fortunately, we don't do this
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* often.
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*/
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udelay(20);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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c1 = mcam_reg_read(mcam, REG_TWSIC1);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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return c1 & (TWSIC1_RVALID|TWSIC1_ERROR);
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}
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static int cafe_smbus_read_data(struct cafe_camera *cam,
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u16 addr, u8 command, u8 *value)
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{
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unsigned int rval;
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unsigned long flags;
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struct mcam_camera *mcam = &cam->mcam;
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spin_lock_irqsave(&mcam->dev_lock, flags);
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rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
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rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
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/*
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* Marvel sez set clkdiv to all 1's for now.
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*/
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rval |= TWSIC0_CLKDIV;
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mcam_reg_write(mcam, REG_TWSIC0, rval);
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(void) mcam_reg_read(mcam, REG_TWSIC1); /* force write */
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rval = TWSIC1_READ | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
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mcam_reg_write(mcam, REG_TWSIC1, rval);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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wait_event_timeout(cam->smbus_wait,
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cafe_smbus_read_done(mcam), CAFE_SMBUS_TIMEOUT);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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rval = mcam_reg_read(mcam, REG_TWSIC1);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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if (rval & TWSIC1_ERROR) {
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cam_err(cam, "SMBUS read (%02x/%02x) error\n", addr, command);
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return -EIO;
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}
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if (!(rval & TWSIC1_RVALID)) {
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cam_err(cam, "SMBUS read (%02x/%02x) timed out\n", addr,
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command);
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return -EIO;
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}
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*value = rval & 0xff;
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return 0;
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}
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/*
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* Perform a transfer over SMBUS. This thing is called under
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* the i2c bus lock, so we shouldn't race with ourselves...
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*/
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static int cafe_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
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unsigned short flags, char rw, u8 command,
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int size, union i2c_smbus_data *data)
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{
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struct cafe_camera *cam = i2c_get_adapdata(adapter);
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int ret = -EINVAL;
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/*
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* This interface would appear to only do byte data ops. OK
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* it can do word too, but the cam chip has no use for that.
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*/
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if (size != I2C_SMBUS_BYTE_DATA) {
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cam_err(cam, "funky xfer size %d\n", size);
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return -EINVAL;
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}
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if (rw == I2C_SMBUS_WRITE)
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ret = cafe_smbus_write_data(cam, addr, command, data->byte);
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else if (rw == I2C_SMBUS_READ)
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ret = cafe_smbus_read_data(cam, addr, command, &data->byte);
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return ret;
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}
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static void cafe_smbus_enable_irq(struct cafe_camera *cam)
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{
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unsigned long flags;
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spin_lock_irqsave(&cam->mcam.dev_lock, flags);
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mcam_reg_set_bit(&cam->mcam, REG_IRQMASK, TWSIIRQS);
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spin_unlock_irqrestore(&cam->mcam.dev_lock, flags);
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}
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static u32 cafe_smbus_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_SMBUS_READ_BYTE_DATA |
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I2C_FUNC_SMBUS_WRITE_BYTE_DATA;
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}
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static struct i2c_algorithm cafe_smbus_algo = {
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.smbus_xfer = cafe_smbus_xfer,
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.functionality = cafe_smbus_func
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};
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static int cafe_smbus_setup(struct cafe_camera *cam)
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{
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struct i2c_adapter *adap = &cam->mcam.i2c_adapter;
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int ret;
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cafe_smbus_enable_irq(cam);
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adap->owner = THIS_MODULE;
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adap->algo = &cafe_smbus_algo;
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strcpy(adap->name, "cafe_ccic");
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adap->dev.parent = &cam->pdev->dev;
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i2c_set_adapdata(adap, cam);
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ret = i2c_add_adapter(adap);
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if (ret)
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printk(KERN_ERR "Unable to register cafe i2c adapter\n");
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return ret;
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}
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static void cafe_smbus_shutdown(struct cafe_camera *cam)
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{
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i2c_del_adapter(&cam->mcam.i2c_adapter);
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}
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/*
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* Controller-level stuff
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*/
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static void cafe_ctlr_init(struct mcam_camera *mcam)
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{
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unsigned long flags;
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spin_lock_irqsave(&mcam->dev_lock, flags);
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/*
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* Added magic to bring up the hardware on the B-Test board
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*/
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mcam_reg_write(mcam, 0x3038, 0x8);
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mcam_reg_write(mcam, 0x315c, 0x80008);
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/*
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* Go through the dance needed to wake the device up.
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* Note that these registers are global and shared
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* with the NAND and SD devices. Interaction between the
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* three still needs to be examined.
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*/
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mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRS|GCSR_MRS); /* Needed? */
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mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRC|GCSR_MRC);
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mcam_reg_write(mcam, REG_GL_CSR, GCSR_SRC|GCSR_MRS);
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/*
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* Here we must wait a bit for the controller to come around.
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*/
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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msleep(5);
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spin_lock_irqsave(&mcam->dev_lock, flags);
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mcam_reg_write(mcam, REG_GL_CSR, GCSR_CCIC_EN|GCSR_SRC|GCSR_MRC);
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mcam_reg_set_bit(mcam, REG_GL_IMASK, GIMSK_CCIC_EN);
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/*
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* Mask all interrupts.
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*/
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mcam_reg_write(mcam, REG_IRQMASK, 0);
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spin_unlock_irqrestore(&mcam->dev_lock, flags);
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}
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static void cafe_ctlr_power_up(struct mcam_camera *mcam)
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{
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/*
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* Part one of the sensor dance: turn the global
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* GPIO signal on.
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*/
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mcam_reg_write(mcam, REG_GL_FCR, GFCR_GPIO_ON);
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mcam_reg_write(mcam, REG_GL_GPIOR, GGPIO_OUT|GGPIO_VAL);
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/*
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* Put the sensor into operational mode (assumes OLPC-style
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* wiring). Control 0 is reset - set to 1 to operate.
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* Control 1 is power down, set to 0 to operate.
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*/
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mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN); /* pwr up, reset */
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mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C0);
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}
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static void cafe_ctlr_power_down(struct mcam_camera *mcam)
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{
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mcam_reg_write(mcam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C1);
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mcam_reg_write(mcam, REG_GL_FCR, GFCR_GPIO_ON);
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mcam_reg_write(mcam, REG_GL_GPIOR, GGPIO_OUT);
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}
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/*
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* The platform interrupt handler.
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*/
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static irqreturn_t cafe_irq(int irq, void *data)
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{
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struct cafe_camera *cam = data;
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struct mcam_camera *mcam = &cam->mcam;
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unsigned int irqs, handled;
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spin_lock(&mcam->dev_lock);
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irqs = mcam_reg_read(mcam, REG_IRQSTAT);
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handled = cam->registered && mccic_irq(mcam, irqs);
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if (irqs & TWSIIRQS) {
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mcam_reg_write(mcam, REG_IRQSTAT, TWSIIRQS);
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wake_up(&cam->smbus_wait);
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handled = 1;
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}
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spin_unlock(&mcam->dev_lock);
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return IRQ_RETVAL(handled);
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}
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/* -------------------------------------------------------------------------- */
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/*
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* PCI interface stuff.
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*/
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static int cafe_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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int ret;
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struct cafe_camera *cam;
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struct mcam_camera *mcam;
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/*
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* Start putting together one of our big camera structures.
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*/
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ret = -ENOMEM;
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cam = kzalloc(sizeof(struct cafe_camera), GFP_KERNEL);
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if (cam == NULL)
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goto out;
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cam->pdev = pdev;
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mcam = &cam->mcam;
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mcam->chip_id = V4L2_IDENT_CAFE;
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spin_lock_init(&mcam->dev_lock);
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init_waitqueue_head(&cam->smbus_wait);
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mcam->plat_power_up = cafe_ctlr_power_up;
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mcam->plat_power_down = cafe_ctlr_power_down;
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mcam->dev = &pdev->dev;
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/*
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* Get set up on the PCI bus.
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*/
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ret = pci_enable_device(pdev);
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if (ret)
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goto out_free;
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pci_set_master(pdev);
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ret = -EIO;
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mcam->regs = pci_iomap(pdev, 0, 0);
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if (!mcam->regs) {
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printk(KERN_ERR "Unable to ioremap cafe-ccic regs\n");
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goto out_disable;
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}
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ret = request_irq(pdev->irq, cafe_irq, IRQF_SHARED, "cafe-ccic", cam);
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if (ret)
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goto out_iounmap;
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/*
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* Initialize the controller and leave it powered up. It will
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* stay that way until the sensor driver shows up.
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*/
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cafe_ctlr_init(mcam);
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cafe_ctlr_power_up(mcam);
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/*
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* Set up I2C/SMBUS communications. We have to drop the mutex here
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* because the sensor could attach in this call chain, leading to
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* unsightly deadlocks.
|
||||
*/
|
||||
ret = cafe_smbus_setup(cam);
|
||||
if (ret)
|
||||
goto out_pdown;
|
||||
|
||||
ret = mccic_register(mcam);
|
||||
if (ret == 0) {
|
||||
cam->registered = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
cafe_smbus_shutdown(cam);
|
||||
out_pdown:
|
||||
cafe_ctlr_power_down(mcam);
|
||||
free_irq(pdev->irq, cam);
|
||||
out_iounmap:
|
||||
pci_iounmap(pdev, mcam->regs);
|
||||
out_disable:
|
||||
pci_disable_device(pdev);
|
||||
out_free:
|
||||
kfree(cam);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Shut down an initialized device
|
||||
*/
|
||||
static void cafe_shutdown(struct cafe_camera *cam)
|
||||
{
|
||||
mccic_shutdown(&cam->mcam);
|
||||
cafe_smbus_shutdown(cam);
|
||||
free_irq(cam->pdev->irq, cam);
|
||||
pci_iounmap(cam->pdev, cam->mcam.regs);
|
||||
}
|
||||
|
||||
|
||||
static void cafe_pci_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
|
||||
struct cafe_camera *cam = to_cam(v4l2_dev);
|
||||
|
||||
if (cam == NULL) {
|
||||
printk(KERN_WARNING "pci_remove on unknown pdev %p\n", pdev);
|
||||
return;
|
||||
}
|
||||
cafe_shutdown(cam);
|
||||
kfree(cam);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
/*
|
||||
* Basic power management.
|
||||
*/
|
||||
static int cafe_pci_suspend(struct pci_dev *pdev, pm_message_t state)
|
||||
{
|
||||
struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
|
||||
struct cafe_camera *cam = to_cam(v4l2_dev);
|
||||
int ret;
|
||||
|
||||
ret = pci_save_state(pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
mccic_suspend(&cam->mcam);
|
||||
pci_disable_device(pdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int cafe_pci_resume(struct pci_dev *pdev)
|
||||
{
|
||||
struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
|
||||
struct cafe_camera *cam = to_cam(v4l2_dev);
|
||||
int ret = 0;
|
||||
|
||||
pci_restore_state(pdev);
|
||||
ret = pci_enable_device(pdev);
|
||||
|
||||
if (ret) {
|
||||
cam_warn(cam, "Unable to re-enable device on resume!\n");
|
||||
return ret;
|
||||
}
|
||||
cafe_ctlr_init(&cam->mcam);
|
||||
return mccic_resume(&cam->mcam);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static struct pci_device_id cafe_ids[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL,
|
||||
PCI_DEVICE_ID_MARVELL_88ALP01_CCIC) },
|
||||
{ 0, }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, cafe_ids);
|
||||
|
||||
static struct pci_driver cafe_pci_driver = {
|
||||
.name = "cafe1000-ccic",
|
||||
.id_table = cafe_ids,
|
||||
.probe = cafe_pci_probe,
|
||||
.remove = cafe_pci_remove,
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = cafe_pci_suspend,
|
||||
.resume = cafe_pci_resume,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
static int __init cafe_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
printk(KERN_NOTICE "Marvell M88ALP01 'CAFE' Camera Controller version %d\n",
|
||||
CAFE_VERSION);
|
||||
ret = pci_register_driver(&cafe_pci_driver);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Unable to register cafe_ccic driver\n");
|
||||
goto out;
|
||||
}
|
||||
ret = 0;
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static void __exit cafe_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&cafe_pci_driver);
|
||||
}
|
||||
|
||||
module_init(cafe_init);
|
||||
module_exit(cafe_exit);
|
||||
|
|
@ -1,166 +0,0 @@
|
|||
/*
|
||||
* Register definitions for the m88alp01 camera interface. Offsets in bytes
|
||||
* as given in the spec.
|
||||
*
|
||||
* Copyright 2006 One Laptop Per Child Association, Inc.
|
||||
*
|
||||
* Written by Jonathan Corbet, corbet@lwn.net.
|
||||
*
|
||||
* This file may be distributed under the terms of the GNU General
|
||||
* Public License, version 2.
|
||||
*/
|
||||
#define REG_Y0BAR 0x00
|
||||
#define REG_Y1BAR 0x04
|
||||
#define REG_Y2BAR 0x08
|
||||
/* ... */
|
||||
|
||||
#define REG_IMGPITCH 0x24 /* Image pitch register */
|
||||
#define IMGP_YP_SHFT 2 /* Y pitch params */
|
||||
#define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
|
||||
#define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
|
||||
#define IMGP_UVP_MASK 0x3ffc0000
|
||||
#define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
|
||||
#define IRQ_EOF0 0x00000001 /* End of frame 0 */
|
||||
#define IRQ_EOF1 0x00000002 /* End of frame 1 */
|
||||
#define IRQ_EOF2 0x00000004 /* End of frame 2 */
|
||||
#define IRQ_SOF0 0x00000008 /* Start of frame 0 */
|
||||
#define IRQ_SOF1 0x00000010 /* Start of frame 1 */
|
||||
#define IRQ_SOF2 0x00000020 /* Start of frame 2 */
|
||||
#define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
|
||||
#define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
|
||||
#define IRQ_TWSIR 0x00020000 /* TWSI read */
|
||||
#define IRQ_TWSIE 0x00040000 /* TWSI error */
|
||||
#define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
|
||||
#define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
|
||||
#define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
|
||||
#define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
|
||||
#define REG_IRQSTAT 0x30 /* IRQ status / clear */
|
||||
|
||||
#define REG_IMGSIZE 0x34 /* Image size */
|
||||
#define IMGSZ_V_MASK 0x1fff0000
|
||||
#define IMGSZ_V_SHIFT 16
|
||||
#define IMGSZ_H_MASK 0x00003fff
|
||||
#define REG_IMGOFFSET 0x38 /* IMage offset */
|
||||
|
||||
#define REG_CTRL0 0x3c /* Control 0 */
|
||||
#define C0_ENABLE 0x00000001 /* Makes the whole thing go */
|
||||
|
||||
/* Mask for all the format bits */
|
||||
#define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
|
||||
|
||||
/* RGB ordering */
|
||||
#define C0_RGB4_RGBX 0x00000000
|
||||
#define C0_RGB4_XRGB 0x00000004
|
||||
#define C0_RGB4_BGRX 0x00000008
|
||||
#define C0_RGB4_XBGR 0x0000000c
|
||||
#define C0_RGB5_RGGB 0x00000000
|
||||
#define C0_RGB5_GRBG 0x00000004
|
||||
#define C0_RGB5_GBRG 0x00000008
|
||||
#define C0_RGB5_BGGR 0x0000000c
|
||||
|
||||
/* Spec has two fields for DIN and DOUT, but they must match, so
|
||||
combine them here. */
|
||||
#define C0_DF_YUV 0x00000000 /* Data is YUV */
|
||||
#define C0_DF_RGB 0x000000a0 /* ... RGB */
|
||||
#define C0_DF_BAYER 0x00000140 /* ... Bayer */
|
||||
/* 8-8-8 must be missing from the below - ask */
|
||||
#define C0_RGBF_565 0x00000000
|
||||
#define C0_RGBF_444 0x00000800
|
||||
#define C0_RGB_BGR 0x00001000 /* Blue comes first */
|
||||
#define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
|
||||
#define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
|
||||
#define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
|
||||
/* Think that 420 packed must be 111 - ask */
|
||||
#define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
|
||||
#define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
|
||||
#define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
|
||||
#define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
|
||||
#define C0_YUVE_XYUV 0x00000000 /* 420: .YUV */
|
||||
#define C0_YUVE_XYVU 0x00010000 /* 420: .YVU */
|
||||
#define C0_YUVE_XUVY 0x00020000 /* 420: .UVY */
|
||||
#define C0_YUVE_XVUY 0x00030000 /* 420: .VUY */
|
||||
/* Bayer bits 18,19 if needed */
|
||||
#define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
|
||||
#define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
|
||||
#define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
|
||||
#define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
|
||||
#define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
|
||||
#define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
|
||||
#define CO_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
|
||||
|
||||
|
||||
#define REG_CTRL1 0x40 /* Control 1 */
|
||||
#define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
|
||||
#define C1_ALPHA_SHFT 20
|
||||
#define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
|
||||
#define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
|
||||
#define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
|
||||
#define C1_DMAB_MASK 0x06000000
|
||||
#define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
|
||||
#define C1_PWRDWN 0x10000000 /* Power down */
|
||||
|
||||
#define REG_CLKCTRL 0x88 /* Clock control */
|
||||
#define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
|
||||
|
||||
#define REG_GPR 0xb4 /* General purpose register. This
|
||||
controls inputs to the power and reset
|
||||
pins on the OV7670 used with OLPC;
|
||||
other deployments could differ. */
|
||||
#define GPR_C1EN 0x00000020 /* Pad 1 (power down) enable */
|
||||
#define GPR_C0EN 0x00000010 /* Pad 0 (reset) enable */
|
||||
#define GPR_C1 0x00000002 /* Control 1 value */
|
||||
/*
|
||||
* Control 0 is wired to reset on OLPC machines. For ov7x sensors,
|
||||
* it is active low, for 0v6x, instead, it's active high. What
|
||||
* fun.
|
||||
*/
|
||||
#define GPR_C0 0x00000001 /* Control 0 value */
|
||||
|
||||
#define REG_TWSIC0 0xb8 /* TWSI (smbus) control 0 */
|
||||
#define TWSIC0_EN 0x00000001 /* TWSI enable */
|
||||
#define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
|
||||
#define TWSIC0_SID 0x000003fc /* Slave ID */
|
||||
#define TWSIC0_SID_SHIFT 2
|
||||
#define TWSIC0_CLKDIV 0x0007fc00 /* Clock divider */
|
||||
#define TWSIC0_MASKACK 0x00400000 /* Mask ack from sensor */
|
||||
#define TWSIC0_OVMAGIC 0x00800000 /* Make it work on OV sensors */
|
||||
|
||||
#define REG_TWSIC1 0xbc /* TWSI control 1 */
|
||||
#define TWSIC1_DATA 0x0000ffff /* Data to/from camchip */
|
||||
#define TWSIC1_ADDR 0x00ff0000 /* Address (register) */
|
||||
#define TWSIC1_ADDR_SHIFT 16
|
||||
#define TWSIC1_READ 0x01000000 /* Set for read op */
|
||||
#define TWSIC1_WSTAT 0x02000000 /* Write status */
|
||||
#define TWSIC1_RVALID 0x04000000 /* Read data valid */
|
||||
#define TWSIC1_ERROR 0x08000000 /* Something screwed up */
|
||||
|
||||
|
||||
#define REG_UBAR 0xc4 /* Upper base address register */
|
||||
|
||||
/*
|
||||
* Here's the weird global control registers which are said to live
|
||||
* way up here.
|
||||
*/
|
||||
#define REG_GL_CSR 0x3004 /* Control/status register */
|
||||
#define GCSR_SRS 0x00000001 /* SW Reset set */
|
||||
#define GCSR_SRC 0x00000002 /* SW Reset clear */
|
||||
#define GCSR_MRS 0x00000004 /* Master reset set */
|
||||
#define GCSR_MRC 0x00000008 /* HW Reset clear */
|
||||
#define GCSR_CCIC_EN 0x00004000 /* CCIC Clock enable */
|
||||
#define REG_GL_IMASK 0x300c /* Interrupt mask register */
|
||||
#define GIMSK_CCIC_EN 0x00000004 /* CCIC Interrupt enable */
|
||||
|
||||
#define REG_GL_FCR 0x3038 /* GPIO functional control register */
|
||||
#define GFCR_GPIO_ON 0x08 /* Camera GPIO enabled */
|
||||
#define REG_GL_GPIOR 0x315c /* GPIO register */
|
||||
#define GGPIO_OUT 0x80000 /* GPIO output */
|
||||
#define GGPIO_VAL 0x00008 /* Output pin value */
|
||||
|
||||
#define REG_LEN REG_GL_IMASK + 4
|
||||
|
||||
|
||||
/*
|
||||
* Useful stuff that probably belongs somewhere global.
|
||||
*/
|
||||
#define VGA_WIDTH 640
|
||||
#define VGA_HEIGHT 480
|
||||
File diff suppressed because it is too large
Load diff
1689
drivers/media/video/marvell-ccic/mcam-core.c
Normal file
1689
drivers/media/video/marvell-ccic/mcam-core.c
Normal file
File diff suppressed because it is too large
Load diff
311
drivers/media/video/marvell-ccic/mcam-core.h
Normal file
311
drivers/media/video/marvell-ccic/mcam-core.h
Normal file
|
|
@ -0,0 +1,311 @@
|
|||
/*
|
||||
* Marvell camera core structures.
|
||||
*
|
||||
* Copyright 2011 Jonathan Corbet corbet@lwn.net
|
||||
*/
|
||||
|
||||
/*
|
||||
* Tracking of streaming I/O buffers.
|
||||
* FIXME doesn't belong in this file
|
||||
*/
|
||||
struct mcam_sio_buffer {
|
||||
struct list_head list;
|
||||
struct v4l2_buffer v4lbuf;
|
||||
char *buffer; /* Where it lives in kernel space */
|
||||
int mapcount;
|
||||
struct mcam_camera *cam;
|
||||
};
|
||||
|
||||
enum mcam_state {
|
||||
S_NOTREADY, /* Not yet initialized */
|
||||
S_IDLE, /* Just hanging around */
|
||||
S_FLAKED, /* Some sort of problem */
|
||||
S_SINGLEREAD, /* In read() */
|
||||
S_SPECREAD, /* Speculative read (for future read()) */
|
||||
S_STREAMING /* Streaming data */
|
||||
};
|
||||
#define MAX_DMA_BUFS 3
|
||||
|
||||
/*
|
||||
* A description of one of our devices.
|
||||
* Locking: controlled by s_mutex. Certain fields, however, require
|
||||
* the dev_lock spinlock; they are marked as such by comments.
|
||||
* dev_lock is also required for access to device registers.
|
||||
*/
|
||||
struct mcam_camera {
|
||||
/*
|
||||
* These fields should be set by the platform code prior to
|
||||
* calling mcam_register().
|
||||
*/
|
||||
struct i2c_adapter i2c_adapter;
|
||||
unsigned char __iomem *regs;
|
||||
spinlock_t dev_lock;
|
||||
struct device *dev; /* For messages, dma alloc */
|
||||
unsigned int chip_id;
|
||||
|
||||
/*
|
||||
* Callbacks from the core to the platform code.
|
||||
*/
|
||||
void (*plat_power_up) (struct mcam_camera *cam);
|
||||
void (*plat_power_down) (struct mcam_camera *cam);
|
||||
|
||||
/*
|
||||
* Everything below here is private to the mcam core and
|
||||
* should not be touched by the platform code.
|
||||
*/
|
||||
struct v4l2_device v4l2_dev;
|
||||
enum mcam_state state;
|
||||
unsigned long flags; /* Buffer status, mainly (dev_lock) */
|
||||
int users; /* How many open FDs */
|
||||
struct file *owner; /* Who has data access (v4l2) */
|
||||
|
||||
/*
|
||||
* Subsystem structures.
|
||||
*/
|
||||
struct video_device vdev;
|
||||
struct v4l2_subdev *sensor;
|
||||
unsigned short sensor_addr;
|
||||
|
||||
struct list_head dev_list; /* link to other devices */
|
||||
|
||||
/* DMA buffers */
|
||||
unsigned int nbufs; /* How many are alloc'd */
|
||||
int next_buf; /* Next to consume (dev_lock) */
|
||||
unsigned int dma_buf_size; /* allocated size */
|
||||
void *dma_bufs[MAX_DMA_BUFS]; /* Internal buffer addresses */
|
||||
dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
|
||||
unsigned int specframes; /* Unconsumed spec frames (dev_lock) */
|
||||
unsigned int sequence; /* Frame sequence number */
|
||||
unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual buffers */
|
||||
|
||||
/* Streaming buffers */
|
||||
unsigned int n_sbufs; /* How many we have */
|
||||
struct mcam_sio_buffer *sb_bufs; /* The array of housekeeping structs */
|
||||
struct list_head sb_avail; /* Available for data (we own) (dev_lock) */
|
||||
struct list_head sb_full; /* With data (user space owns) (dev_lock) */
|
||||
struct tasklet_struct s_tasklet;
|
||||
|
||||
/* Current operating parameters */
|
||||
u32 sensor_type; /* Currently ov7670 only */
|
||||
struct v4l2_pix_format pix_format;
|
||||
enum v4l2_mbus_pixelcode mbus_code;
|
||||
|
||||
/* Locks */
|
||||
struct mutex s_mutex; /* Access to this structure */
|
||||
|
||||
/* Misc */
|
||||
wait_queue_head_t iowait; /* Waiting on frame data */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Register I/O functions. These are here because the platform code
|
||||
* may legitimately need to mess with the register space.
|
||||
*/
|
||||
/*
|
||||
* Device register I/O
|
||||
*/
|
||||
static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
|
||||
unsigned int val)
|
||||
{
|
||||
iowrite32(val, cam->regs + reg);
|
||||
}
|
||||
|
||||
static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
|
||||
unsigned int reg)
|
||||
{
|
||||
return ioread32(cam->regs + reg);
|
||||
}
|
||||
|
||||
|
||||
static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
|
||||
unsigned int val, unsigned int mask)
|
||||
{
|
||||
unsigned int v = mcam_reg_read(cam, reg);
|
||||
|
||||
v = (v & ~mask) | (val & mask);
|
||||
mcam_reg_write(cam, reg, v);
|
||||
}
|
||||
|
||||
static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
|
||||
unsigned int reg, unsigned int val)
|
||||
{
|
||||
mcam_reg_write_mask(cam, reg, 0, val);
|
||||
}
|
||||
|
||||
static inline void mcam_reg_set_bit(struct mcam_camera *cam,
|
||||
unsigned int reg, unsigned int val)
|
||||
{
|
||||
mcam_reg_write_mask(cam, reg, val, val);
|
||||
}
|
||||
|
||||
/*
|
||||
* Functions for use by platform code.
|
||||
*/
|
||||
int mccic_register(struct mcam_camera *cam);
|
||||
int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
|
||||
void mccic_shutdown(struct mcam_camera *cam);
|
||||
#ifdef CONFIG_PM
|
||||
void mccic_suspend(struct mcam_camera *cam);
|
||||
int mccic_resume(struct mcam_camera *cam);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Register definitions for the m88alp01 camera interface. Offsets in bytes
|
||||
* as given in the spec.
|
||||
*/
|
||||
#define REG_Y0BAR 0x00
|
||||
#define REG_Y1BAR 0x04
|
||||
#define REG_Y2BAR 0x08
|
||||
/* ... */
|
||||
|
||||
#define REG_IMGPITCH 0x24 /* Image pitch register */
|
||||
#define IMGP_YP_SHFT 2 /* Y pitch params */
|
||||
#define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
|
||||
#define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
|
||||
#define IMGP_UVP_MASK 0x3ffc0000
|
||||
#define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
|
||||
#define IRQ_EOF0 0x00000001 /* End of frame 0 */
|
||||
#define IRQ_EOF1 0x00000002 /* End of frame 1 */
|
||||
#define IRQ_EOF2 0x00000004 /* End of frame 2 */
|
||||
#define IRQ_SOF0 0x00000008 /* Start of frame 0 */
|
||||
#define IRQ_SOF1 0x00000010 /* Start of frame 1 */
|
||||
#define IRQ_SOF2 0x00000020 /* Start of frame 2 */
|
||||
#define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
|
||||
#define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
|
||||
#define IRQ_TWSIR 0x00020000 /* TWSI read */
|
||||
#define IRQ_TWSIE 0x00040000 /* TWSI error */
|
||||
#define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
|
||||
#define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
|
||||
#define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
|
||||
#define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
|
||||
#define REG_IRQSTAT 0x30 /* IRQ status / clear */
|
||||
|
||||
#define REG_IMGSIZE 0x34 /* Image size */
|
||||
#define IMGSZ_V_MASK 0x1fff0000
|
||||
#define IMGSZ_V_SHIFT 16
|
||||
#define IMGSZ_H_MASK 0x00003fff
|
||||
#define REG_IMGOFFSET 0x38 /* IMage offset */
|
||||
|
||||
#define REG_CTRL0 0x3c /* Control 0 */
|
||||
#define C0_ENABLE 0x00000001 /* Makes the whole thing go */
|
||||
|
||||
/* Mask for all the format bits */
|
||||
#define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
|
||||
|
||||
/* RGB ordering */
|
||||
#define C0_RGB4_RGBX 0x00000000
|
||||
#define C0_RGB4_XRGB 0x00000004
|
||||
#define C0_RGB4_BGRX 0x00000008
|
||||
#define C0_RGB4_XBGR 0x0000000c
|
||||
#define C0_RGB5_RGGB 0x00000000
|
||||
#define C0_RGB5_GRBG 0x00000004
|
||||
#define C0_RGB5_GBRG 0x00000008
|
||||
#define C0_RGB5_BGGR 0x0000000c
|
||||
|
||||
/* Spec has two fields for DIN and DOUT, but they must match, so
|
||||
combine them here. */
|
||||
#define C0_DF_YUV 0x00000000 /* Data is YUV */
|
||||
#define C0_DF_RGB 0x000000a0 /* ... RGB */
|
||||
#define C0_DF_BAYER 0x00000140 /* ... Bayer */
|
||||
/* 8-8-8 must be missing from the below - ask */
|
||||
#define C0_RGBF_565 0x00000000
|
||||
#define C0_RGBF_444 0x00000800
|
||||
#define C0_RGB_BGR 0x00001000 /* Blue comes first */
|
||||
#define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
|
||||
#define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
|
||||
#define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
|
||||
/* Think that 420 packed must be 111 - ask */
|
||||
#define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
|
||||
#define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
|
||||
#define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
|
||||
#define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
|
||||
#define C0_YUVE_XYUV 0x00000000 /* 420: .YUV */
|
||||
#define C0_YUVE_XYVU 0x00010000 /* 420: .YVU */
|
||||
#define C0_YUVE_XUVY 0x00020000 /* 420: .UVY */
|
||||
#define C0_YUVE_XVUY 0x00030000 /* 420: .VUY */
|
||||
/* Bayer bits 18,19 if needed */
|
||||
#define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
|
||||
#define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
|
||||
#define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
|
||||
#define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
|
||||
#define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
|
||||
#define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
|
||||
#define CO_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
|
||||
|
||||
|
||||
#define REG_CTRL1 0x40 /* Control 1 */
|
||||
#define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
|
||||
#define C1_ALPHA_SHFT 20
|
||||
#define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
|
||||
#define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
|
||||
#define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
|
||||
#define C1_DMAB_MASK 0x06000000
|
||||
#define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
|
||||
#define C1_PWRDWN 0x10000000 /* Power down */
|
||||
|
||||
#define REG_CLKCTRL 0x88 /* Clock control */
|
||||
#define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
|
||||
|
||||
#define REG_GPR 0xb4 /* General purpose register. This
|
||||
controls inputs to the power and reset
|
||||
pins on the OV7670 used with OLPC;
|
||||
other deployments could differ. */
|
||||
#define GPR_C1EN 0x00000020 /* Pad 1 (power down) enable */
|
||||
#define GPR_C0EN 0x00000010 /* Pad 0 (reset) enable */
|
||||
#define GPR_C1 0x00000002 /* Control 1 value */
|
||||
/*
|
||||
* Control 0 is wired to reset on OLPC machines. For ov7x sensors,
|
||||
* it is active low, for 0v6x, instead, it's active high. What
|
||||
* fun.
|
||||
*/
|
||||
#define GPR_C0 0x00000001 /* Control 0 value */
|
||||
|
||||
#define REG_TWSIC0 0xb8 /* TWSI (smbus) control 0 */
|
||||
#define TWSIC0_EN 0x00000001 /* TWSI enable */
|
||||
#define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
|
||||
#define TWSIC0_SID 0x000003fc /* Slave ID */
|
||||
#define TWSIC0_SID_SHIFT 2
|
||||
#define TWSIC0_CLKDIV 0x0007fc00 /* Clock divider */
|
||||
#define TWSIC0_MASKACK 0x00400000 /* Mask ack from sensor */
|
||||
#define TWSIC0_OVMAGIC 0x00800000 /* Make it work on OV sensors */
|
||||
|
||||
#define REG_TWSIC1 0xbc /* TWSI control 1 */
|
||||
#define TWSIC1_DATA 0x0000ffff /* Data to/from camchip */
|
||||
#define TWSIC1_ADDR 0x00ff0000 /* Address (register) */
|
||||
#define TWSIC1_ADDR_SHIFT 16
|
||||
#define TWSIC1_READ 0x01000000 /* Set for read op */
|
||||
#define TWSIC1_WSTAT 0x02000000 /* Write status */
|
||||
#define TWSIC1_RVALID 0x04000000 /* Read data valid */
|
||||
#define TWSIC1_ERROR 0x08000000 /* Something screwed up */
|
||||
|
||||
|
||||
#define REG_UBAR 0xc4 /* Upper base address register */
|
||||
|
||||
/*
|
||||
* Here's the weird global control registers which are said to live
|
||||
* way up here.
|
||||
*/
|
||||
#define REG_GL_CSR 0x3004 /* Control/status register */
|
||||
#define GCSR_SRS 0x00000001 /* SW Reset set */
|
||||
#define GCSR_SRC 0x00000002 /* SW Reset clear */
|
||||
#define GCSR_MRS 0x00000004 /* Master reset set */
|
||||
#define GCSR_MRC 0x00000008 /* HW Reset clear */
|
||||
#define GCSR_CCIC_EN 0x00004000 /* CCIC Clock enable */
|
||||
#define REG_GL_IMASK 0x300c /* Interrupt mask register */
|
||||
#define GIMSK_CCIC_EN 0x00000004 /* CCIC Interrupt enable */
|
||||
|
||||
#define REG_GL_FCR 0x3038 /* GPIO functional control register */
|
||||
#define GFCR_GPIO_ON 0x08 /* Camera GPIO enabled */
|
||||
#define REG_GL_GPIOR 0x315c /* GPIO register */
|
||||
#define GGPIO_OUT 0x80000 /* GPIO output */
|
||||
#define GGPIO_VAL 0x00008 /* Output pin value */
|
||||
|
||||
#define REG_LEN (REG_GL_IMASK + 4)
|
||||
|
||||
|
||||
/*
|
||||
* Useful stuff that probably belongs somewhere global.
|
||||
*/
|
||||
#define VGA_WIDTH 640
|
||||
#define VGA_HEIGHT 480
|
||||
Loading…
Reference in a new issue