ntb: Adding split BAR support for Haswell platforms
On the Haswell platform, a split BAR option to allow creation of 2 32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this new option. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
This commit is contained in:
Dave Jiang
Jon Mason
parent
069684e888
commit
ab760a0c56
3 changed files with 210 additions and 60 deletions
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@ -84,8 +84,8 @@ static struct dentry *debugfs_dir;
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#define BWD_LINK_RECOVERY_TIME 500
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/* Translate memory window 0,1 to BAR 2,4 */
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#define MW_TO_BAR(mw) (mw * NTB_MAX_NUM_MW + 2)
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/* Translate memory window 0,1,2 to BAR 2,4,5 */
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#define MW_TO_BAR(mw) (mw == 0 ? 2 : (mw == 1 ? 4 : 5))
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static const struct pci_device_id ntb_pci_tbl[] = {
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{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
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@ -506,9 +506,15 @@ void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
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case NTB_BAR_23:
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writeq(addr, ndev->reg_ofs.bar2_xlat);
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break;
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case NTB_BAR_45:
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case NTB_BAR_4:
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if (ndev->split_bar)
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writel(addr, ndev->reg_ofs.bar4_xlat);
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else
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writeq(addr, ndev->reg_ofs.bar4_xlat);
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break;
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case NTB_BAR_5:
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writel(addr, ndev->reg_ofs.bar5_xlat);
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break;
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}
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}
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@ -729,6 +735,9 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
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ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
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ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
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if (ndev->split_bar)
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ndev->reg_ofs.bar5_xlat =
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ndev->reg_base + SNB_SBAR5XLAT_OFFSET;
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ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
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/* There is a Xeon hardware errata related to writes to
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@ -738,14 +747,15 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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* scratch pad registers on the remote system.
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*/
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if (ndev->wa_flags & WA_SNB_ERR) {
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if (!ndev->mw[1].bar_sz)
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if (!ndev->mw[ndev->limits.max_mw - 1].bar_sz)
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return -EINVAL;
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ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
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ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
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ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
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ndev->reg_ofs.spad_write =
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ndev->mw[ndev->limits.max_mw - 1].vbase +
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SNB_SPAD_OFFSET;
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ndev->reg_ofs.rdb = ndev->mw[1].vbase +
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ndev->reg_ofs.rdb =
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ndev->mw[ndev->limits.max_mw - 1].vbase +
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SNB_PDOORBELL_OFFSET;
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/* Set the Limit register to 4k, the minimum size, to
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@ -759,9 +769,9 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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* the driver defaults, but write the Limit registers
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* first just in case.
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*/
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} else {
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ndev->limits.max_mw = SNB_MAX_MW;
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ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
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} else {
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/* HW Errata on bit 14 of b2bdoorbell register. Writes
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* will not be mirrored to the remote system. Shrink
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* the number of bits by one, since bit 14 is the last
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@ -774,7 +784,8 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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SNB_B2B_DOORBELL_OFFSET;
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/* Disable the Limit register, just incase it is set to
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* something silly
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* something silly. A 64bit write should handle it
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* regardless of whether it has a split BAR or not.
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*/
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writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
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/* HW errata on the Limit registers. They can only be
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@ -783,6 +794,10 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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* the driver defaults, but write the Limit registers
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* first just in case.
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*/
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if (ndev->split_bar)
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ndev->limits.max_mw = HSX_SPLITBAR_MAX_MW;
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else
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ndev->limits.max_mw = SNB_MAX_MW;
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}
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/* The Xeon errata workaround requires setting SBAR Base
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@ -796,8 +811,18 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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else {
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writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
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if (ndev->split_bar) {
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writel(SNB_MBAR4_DSD_ADDR,
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ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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writel(SNB_MBAR5_DSD_ADDR,
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ndev->reg_base +
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SNB_PBAR5XLAT_OFFSET);
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} else
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writeq(SNB_MBAR4_DSD_ADDR,
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ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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/* B2B_XLAT_OFFSET is a 64bit register, but can
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* only take 32bit writes
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*/
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@ -811,7 +836,13 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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SNB_SBAR0BASE_OFFSET);
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writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
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SNB_SBAR2BASE_OFFSET);
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writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
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if (ndev->split_bar) {
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writel(SNB_MBAR4_USD_ADDR, ndev->reg_base +
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SNB_SBAR4BASE_OFFSET);
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writel(SNB_MBAR5_USD_ADDR, ndev->reg_base +
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SNB_SBAR5BASE_OFFSET);
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} else
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writeq(SNB_MBAR4_USD_ADDR, ndev->reg_base +
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SNB_SBAR4BASE_OFFSET);
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} else {
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writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
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@ -820,9 +851,20 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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else {
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writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
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if (ndev->split_bar) {
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writel(SNB_MBAR4_USD_ADDR,
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ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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/* B2B_XLAT_OFFSET is a 64bit register, but can
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writel(SNB_MBAR5_USD_ADDR,
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ndev->reg_base +
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SNB_PBAR5XLAT_OFFSET);
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} else
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writeq(SNB_MBAR4_USD_ADDR,
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ndev->reg_base +
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SNB_PBAR4XLAT_OFFSET);
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/*
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* B2B_XLAT_OFFSET is a 64bit register, but can
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* only take 32bit writes
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*/
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writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
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@ -834,8 +876,15 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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SNB_SBAR0BASE_OFFSET);
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writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
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SNB_SBAR2BASE_OFFSET);
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writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
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if (ndev->split_bar) {
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writel(SNB_MBAR4_DSD_ADDR, ndev->reg_base +
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SNB_SBAR4BASE_OFFSET);
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writel(SNB_MBAR5_DSD_ADDR, ndev->reg_base +
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SNB_SBAR5BASE_OFFSET);
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} else
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writeq(SNB_MBAR4_DSD_ADDR, ndev->reg_base +
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SNB_SBAR4BASE_OFFSET);
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}
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break;
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case NTB_CONN_RP:
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@ -865,6 +914,11 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
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ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
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ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
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if (ndev->split_bar) {
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ndev->reg_ofs.bar5_xlat =
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ndev->reg_base + SNB_SBAR5XLAT_OFFSET;
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ndev->limits.max_mw = HSX_SPLITBAR_MAX_MW;
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} else
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ndev->limits.max_mw = SNB_MAX_MW;
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break;
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case NTB_CONN_TRANSPARENT:
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@ -892,6 +946,11 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
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ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
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ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
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if (ndev->split_bar) {
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ndev->reg_ofs.bar5_xlat =
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ndev->reg_base + SNB_PBAR5XLAT_OFFSET;
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ndev->limits.max_mw = HSX_SPLITBAR_MAX_MW;
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} else
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ndev->limits.max_mw = SNB_MAX_MW;
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break;
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default:
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@ -1499,7 +1558,11 @@ static void ntb_hw_link_up(struct ntb_device *ndev)
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ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
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ntb_cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK);
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ntb_cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP;
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ntb_cntl |= NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP;
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ntb_cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP;
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if (ndev->split_bar)
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ntb_cntl |= NTB_CNTL_P2S_BAR5_SNOOP |
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NTB_CNTL_S2P_BAR5_SNOOP;
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writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
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}
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}
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@ -1516,14 +1579,26 @@ static void ntb_hw_link_down(struct ntb_device *ndev)
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/* Bring NTB link down */
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ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
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ntb_cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP);
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ntb_cntl &= ~(NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP);
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ntb_cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP);
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if (ndev->split_bar)
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ntb_cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP |
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NTB_CNTL_S2P_BAR5_SNOOP);
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ntb_cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK;
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writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
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}
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static void ntb_max_mw_detect(struct ntb_device *ndev)
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{
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if (ndev->split_bar)
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ndev->limits.max_mw = HSX_SPLITBAR_MAX_MW;
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else
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ndev->limits.max_mw = SNB_MAX_MW;
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}
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static int ntb_xeon_detect(struct ntb_device *ndev)
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{
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int rc;
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int rc, bars_mask;
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u32 bars;
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u8 ppd;
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ndev->hw_type = SNB_HW;
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@ -1537,6 +1612,8 @@ static int ntb_xeon_detect(struct ntb_device *ndev)
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else
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ndev->dev_type = NTB_DEV_DSD;
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ndev->split_bar = (ppd & SNB_PPD_SPLIT_BAR) ? 1 : 0;
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switch (ppd & SNB_PPD_CONN_TYPE) {
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case NTB_CONN_B2B:
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dev_info(&ndev->pdev->dev, "Conn Type = B2B\n");
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@ -1555,12 +1632,25 @@ static int ntb_xeon_detect(struct ntb_device *ndev)
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* NTB. We will just force correct here.
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*/
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ndev->dev_type = NTB_DEV_USD;
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/*
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* This is a way for transparent BAR to figure out if we
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* are doing split BAR or not. There is no way for the hw
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* on the transparent side to know and set the PPD.
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*/
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bars_mask = pci_select_bars(ndev->pdev, IORESOURCE_MEM);
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bars = hweight32(bars_mask);
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if (bars == (HSX_SPLITBAR_MAX_MW + 1))
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ndev->split_bar = 1;
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break;
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default:
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dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", ppd);
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return -ENODEV;
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}
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ntb_max_mw_detect(ndev);
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return 0;
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}
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@ -1638,22 +1728,50 @@ static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (rc)
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goto err;
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rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
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if (rc)
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ndev->mw = kcalloc(ndev->limits.max_mw, sizeof(struct ntb_mw),
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GFP_KERNEL);
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if (!ndev->mw) {
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rc = -ENOMEM;
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goto err1;
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}
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if (ndev->split_bar)
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rc = pci_request_selected_regions(pdev, NTB_SPLITBAR_MASK,
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KBUILD_MODNAME);
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else
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rc = pci_request_selected_regions(pdev, NTB_BAR_MASK,
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KBUILD_MODNAME);
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if (rc)
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goto err2;
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ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
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if (!ndev->reg_base) {
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dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
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rc = -EIO;
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goto err2;
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goto err3;
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}
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for (i = 0; i < NTB_MAX_NUM_MW; i++) {
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for (i = 0; i < ndev->limits.max_mw; i++) {
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ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
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/*
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* with the errata we need to steal last of the memory
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* windows for workarounds and they point to MMIO registers.
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*/
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if ((ndev->wa_flags & WA_SNB_ERR) &&
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(i == (ndev->limits.max_mw - 1))) {
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ndev->mw[i].vbase =
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ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
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ioremap_nocache(pci_resource_start(pdev,
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MW_TO_BAR(i)),
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ndev->mw[i].bar_sz);
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} else {
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ndev->mw[i].vbase =
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ioremap_wc(pci_resource_start(pdev,
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MW_TO_BAR(i)),
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ndev->mw[i].bar_sz);
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}
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dev_info(&pdev->dev, "MW %d size %llu\n", i,
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(unsigned long long) ndev->mw[i].bar_sz);
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if (!ndev->mw[i].vbase) {
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@ -1668,7 +1786,7 @@ static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (rc) {
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (rc)
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goto err3;
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goto err4;
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dev_warn(&pdev->dev, "Cannot DMA highmem\n");
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}
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@ -1677,22 +1795,22 @@ static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (rc) {
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rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (rc)
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goto err3;
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goto err4;
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dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
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}
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rc = ntb_device_setup(ndev);
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if (rc)
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goto err3;
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goto err4;
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rc = ntb_create_callbacks(ndev);
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if (rc)
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goto err4;
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goto err5;
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rc = ntb_setup_interrupts(ndev);
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if (rc)
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goto err5;
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goto err6;
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/* The scratchpad registers keep the values between rmmod/insmod,
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* blast them now
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@ -1704,24 +1822,29 @@ static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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rc = ntb_transport_init(pdev);
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if (rc)
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goto err6;
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goto err7;
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ntb_hw_link_up(ndev);
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return 0;
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err6:
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err7:
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ntb_free_interrupts(ndev);
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err5:
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err6:
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ntb_free_callbacks(ndev);
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err4:
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err5:
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ntb_device_free(ndev);
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err3:
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err4:
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for (i--; i >= 0; i--)
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iounmap(ndev->mw[i].vbase);
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iounmap(ndev->reg_base);
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err2:
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err3:
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if (ndev->split_bar)
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pci_release_selected_regions(pdev, NTB_SPLITBAR_MASK);
|
||||
else
|
||||
pci_release_selected_regions(pdev, NTB_BAR_MASK);
|
||||
err2:
|
||||
kfree(ndev->mw);
|
||||
err1:
|
||||
pci_disable_device(pdev);
|
||||
err:
|
||||
|
|
@ -1745,10 +1868,18 @@ static void ntb_pci_remove(struct pci_dev *pdev)
|
|||
ntb_free_callbacks(ndev);
|
||||
ntb_device_free(ndev);
|
||||
|
||||
for (i = 0; i < NTB_MAX_NUM_MW; i++)
|
||||
/* need to reset max_mw limits so we can unmap properly */
|
||||
if (ndev->hw_type == SNB_HW)
|
||||
ntb_max_mw_detect(ndev);
|
||||
|
||||
for (i = 0; i < ndev->limits.max_mw; i++)
|
||||
iounmap(ndev->mw[i].vbase);
|
||||
|
||||
kfree(ndev->mw);
|
||||
iounmap(ndev->reg_base);
|
||||
if (ndev->split_bar)
|
||||
pci_release_selected_regions(pdev, NTB_SPLITBAR_MASK);
|
||||
else
|
||||
pci_release_selected_regions(pdev, NTB_BAR_MASK);
|
||||
pci_disable_device(pdev);
|
||||
ntb_free_debugfs(ndev);
|
||||
|
|
|
|||
|
|
@ -78,14 +78,16 @@ static inline void writeq(u64 val, void __iomem *addr)
|
|||
|
||||
#define NTB_BAR_MMIO 0
|
||||
#define NTB_BAR_23 2
|
||||
#define NTB_BAR_45 4
|
||||
#define NTB_BAR_4 4
|
||||
#define NTB_BAR_5 5
|
||||
|
||||
#define NTB_BAR_MASK ((1 << NTB_BAR_MMIO) | (1 << NTB_BAR_23) |\
|
||||
(1 << NTB_BAR_45))
|
||||
(1 << NTB_BAR_4))
|
||||
#define NTB_SPLITBAR_MASK ((1 << NTB_BAR_MMIO) | (1 << NTB_BAR_23) |\
|
||||
(1 << NTB_BAR_4) | (1 << NTB_BAR_5))
|
||||
|
||||
#define NTB_HB_TIMEOUT msecs_to_jiffies(1000)
|
||||
|
||||
#define NTB_MAX_NUM_MW 2
|
||||
|
||||
enum ntb_hw_event {
|
||||
NTB_EVENT_SW_EVENT0 = 0,
|
||||
NTB_EVENT_SW_EVENT1,
|
||||
|
|
@ -115,7 +117,7 @@ struct ntb_device {
|
|||
struct pci_dev *pdev;
|
||||
struct msix_entry *msix_entries;
|
||||
void __iomem *reg_base;
|
||||
struct ntb_mw mw[NTB_MAX_NUM_MW];
|
||||
struct ntb_mw *mw;
|
||||
struct {
|
||||
unsigned char max_mw;
|
||||
unsigned char max_spads;
|
||||
|
|
@ -128,6 +130,7 @@ struct ntb_device {
|
|||
void __iomem *rdb;
|
||||
void __iomem *bar2_xlat;
|
||||
void __iomem *bar4_xlat;
|
||||
void __iomem *bar5_xlat;
|
||||
void __iomem *spad_write;
|
||||
void __iomem *spad_read;
|
||||
void __iomem *lnk_cntl;
|
||||
|
|
@ -147,6 +150,7 @@ struct ntb_device {
|
|||
unsigned char link_width;
|
||||
unsigned char link_speed;
|
||||
unsigned char link_status;
|
||||
unsigned char split_bar;
|
||||
|
||||
struct delayed_work hb_timer;
|
||||
unsigned long last_ts;
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@
|
|||
#define SNB_MAX_DB_BITS 15
|
||||
#define SNB_LINK_DB 15
|
||||
#define SNB_DB_BITS_PER_VEC 5
|
||||
#define HSX_SPLITBAR_MAX_MW 3
|
||||
#define SNB_MAX_MW 2
|
||||
#define SNB_ERRATA_MAX_MW 1
|
||||
|
||||
|
|
@ -72,15 +73,20 @@
|
|||
|
||||
#define SNB_PBAR2LMT_OFFSET 0x0000
|
||||
#define SNB_PBAR4LMT_OFFSET 0x0008
|
||||
#define SNB_PBAR5LMT_OFFSET 0x000C
|
||||
#define SNB_PBAR2XLAT_OFFSET 0x0010
|
||||
#define SNB_PBAR4XLAT_OFFSET 0x0018
|
||||
#define SNB_PBAR5XLAT_OFFSET 0x001C
|
||||
#define SNB_SBAR2LMT_OFFSET 0x0020
|
||||
#define SNB_SBAR4LMT_OFFSET 0x0028
|
||||
#define SNB_SBAR5LMT_OFFSET 0x002C
|
||||
#define SNB_SBAR2XLAT_OFFSET 0x0030
|
||||
#define SNB_SBAR4XLAT_OFFSET 0x0038
|
||||
#define SNB_SBAR5XLAT_OFFSET 0x003C
|
||||
#define SNB_SBAR0BASE_OFFSET 0x0040
|
||||
#define SNB_SBAR2BASE_OFFSET 0x0048
|
||||
#define SNB_SBAR4BASE_OFFSET 0x0050
|
||||
#define SNB_SBAR5BASE_OFFSET 0x0054
|
||||
#define SNB_NTBCNTL_OFFSET 0x0058
|
||||
#define SNB_SBDF_OFFSET 0x005C
|
||||
#define SNB_PDOORBELL_OFFSET 0x0060
|
||||
|
|
@ -96,12 +102,18 @@
|
|||
#define SNB_B2B_XLAT_OFFSETL 0x0144
|
||||
#define SNB_B2B_XLAT_OFFSETU 0x0148
|
||||
|
||||
#define SNB_MBAR01_USD_ADDR 0x000000210000000CULL
|
||||
#define SNB_MBAR23_USD_ADDR 0x000000410000000CULL
|
||||
#define SNB_MBAR45_USD_ADDR 0x000000810000000CULL
|
||||
#define SNB_MBAR01_DSD_ADDR 0x000000200000000CULL
|
||||
#define SNB_MBAR23_DSD_ADDR 0x000000400000000CULL
|
||||
#define SNB_MBAR45_DSD_ADDR 0x000000800000000CULL
|
||||
/*
|
||||
* The addresses are setup so the 32bit BARs can function. Thus
|
||||
* the addresses are all in 32bit space
|
||||
*/
|
||||
#define SNB_MBAR01_USD_ADDR 0x000000002100000CULL
|
||||
#define SNB_MBAR23_USD_ADDR 0x000000004100000CULL
|
||||
#define SNB_MBAR4_USD_ADDR 0x000000008100000CULL
|
||||
#define SNB_MBAR5_USD_ADDR 0x00000000A100000CULL
|
||||
#define SNB_MBAR01_DSD_ADDR 0x000000002000000CULL
|
||||
#define SNB_MBAR23_DSD_ADDR 0x000000004000000CULL
|
||||
#define SNB_MBAR4_DSD_ADDR 0x000000008000000CULL
|
||||
#define SNB_MBAR5_DSD_ADDR 0x00000000A000000CULL
|
||||
|
||||
#define BWD_MSIX_CNT 34
|
||||
#define BWD_MAX_SPADS 16
|
||||
|
|
@ -150,13 +162,16 @@
|
|||
#define NTB_CNTL_LINK_DISABLE (1 << 1)
|
||||
#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
|
||||
#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
|
||||
#define NTB_CNTL_S2P_BAR45_SNOOP (1 << 6)
|
||||
#define NTB_CNTL_P2S_BAR45_SNOOP (1 << 8)
|
||||
#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
|
||||
#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
|
||||
#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
|
||||
#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
|
||||
#define BWD_CNTL_LINK_DOWN (1 << 16)
|
||||
|
||||
#define NTB_PPD_OFFSET 0x00D4
|
||||
#define SNB_PPD_CONN_TYPE 0x0003
|
||||
#define SNB_PPD_DEV_TYPE 0x0010
|
||||
#define SNB_PPD_SPLIT_BAR (1 << 6)
|
||||
#define BWD_PPD_INIT_LINK 0x0008
|
||||
#define BWD_PPD_CONN_TYPE 0x0300
|
||||
#define BWD_PPD_DEV_TYPE 0x1000
|
||||
|
|
|
|||
Loading…
Reference in a new issue