arm-cci: Abstract out the PMU counter details
Adds the PMU model specific counters to the PMU model abstraction to make it easier to add a new PMU. The patch cleans up the naming convention used all over the code. e.g, CCI_PMU_MAX_HW_EVENTS => maximum number of events that can be counted at any time, which is in fact the maximum number of counters available. Change all such namings to use 'counters' instead of events. This patch also abstracts the following: 1) Size of a PMU event counter area. 2) Maximum number of programmable counters supported by the PMU model 3) Number of counters which counts fixed events (e.g, cycle counter on CCI-400). Also changes some of the static allocation of the data structures to dynamic, to accommodate the number of events supported by a PMU. Gets rid ofthe CCI_PMU_* defines for the model. All such data should be accessed via the model abstraction. Limits the number of counters to the maximum supported by the 'model'. Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Suzuki K. Poulose
Arnd Bergmann
parent
a1a076d767
commit
ab5b316d4b
1 changed files with 99 additions and 36 deletions
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@ -77,15 +77,17 @@ static const struct of_device_id arm_cci_matches[] = {
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#define CCI_PMU_OVRFLW_FLAG 1
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#define CCI_PMU_CNTR_BASE(idx) ((idx) * SZ_4K)
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#define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
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#define CCI_PMU_CNTR_SIZE(model) ((model)->cntr_size)
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#define CCI_PMU_CNTR_BASE(model, idx) ((idx) * CCI_PMU_CNTR_SIZE(model))
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#define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
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#define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1)
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#define CCI_PMU_EVENT_MASK 0xffUL
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#define CCI_PMU_EVENT_SOURCE(event) ((event >> 5) & 0x7)
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#define CCI_PMU_EVENT_CODE(event) (event & 0x1f)
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#define CCI_PMU_MAX_HW_EVENTS 5 /* CCI PMU has 4 counters + 1 cycle counter */
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#define CCI_PMU_MAX_HW_CNTRS(model) \
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((model)->num_hw_cntrs + (model)->fixed_hw_cntrs)
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/* Types of interfaces that can generate events */
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enum {
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@ -100,13 +102,22 @@ struct event_range {
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};
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struct cci_pmu_hw_events {
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struct perf_event *events[CCI_PMU_MAX_HW_EVENTS];
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unsigned long used_mask[BITS_TO_LONGS(CCI_PMU_MAX_HW_EVENTS)];
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struct perf_event **events;
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unsigned long *used_mask;
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raw_spinlock_t pmu_lock;
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};
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/*
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* struct cci_pmu_model:
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* @fixed_hw_cntrs - Number of fixed event counters
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* @num_hw_cntrs - Maximum number of programmable event counters
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* @cntr_size - Size of an event counter mapping
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*/
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struct cci_pmu_model {
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char *name;
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u32 fixed_hw_cntrs;
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u32 num_hw_cntrs;
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u32 cntr_size;
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struct event_range event_ranges[CCI_IF_MAX];
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};
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@ -116,12 +127,12 @@ struct cci_pmu {
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void __iomem *base;
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struct pmu pmu;
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int nr_irqs;
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int irqs[CCI_PMU_MAX_HW_EVENTS];
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int *irqs;
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unsigned long active_irqs;
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const struct cci_pmu_model *model;
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struct cci_pmu_hw_events hw_events;
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struct platform_device *plat_device;
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int num_events;
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int num_cntrs;
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atomic_t active_events;
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struct mutex reserve_mutex;
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struct notifier_block cpu_nb;
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@ -155,7 +166,6 @@ enum cci400_perf_events {
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#define CCI_PMU_CYCLE_CNTR_IDX 0
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#define CCI_PMU_CNTR0_IDX 1
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#define CCI_PMU_CNTR_LAST(cci_pmu) (CCI_PMU_CYCLE_CNTR_IDX + cci_pmu->num_events - 1)
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/*
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* CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
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@ -235,20 +245,20 @@ static const struct cci_pmu_model *probe_cci_model(struct platform_device *pdev)
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static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx)
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{
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return CCI_PMU_CYCLE_CNTR_IDX <= idx &&
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idx <= CCI_PMU_CNTR_LAST(cci_pmu);
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return 0 <= idx && idx <= CCI_PMU_CNTR_LAST(cci_pmu);
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}
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static u32 pmu_read_register(struct cci_pmu *cci_pmu, int idx, unsigned int offset)
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{
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return readl_relaxed(cci_pmu->base + CCI_PMU_CNTR_BASE(idx) + offset);
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return readl_relaxed(cci_pmu->base +
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CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset);
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}
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static void pmu_write_register(struct cci_pmu *cci_pmu, u32 value,
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int idx, unsigned int offset)
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{
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return writel_relaxed(value, cci_pmu->base +
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CCI_PMU_CNTR_BASE(idx) + offset);
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CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset);
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}
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static void pmu_disable_counter(struct cci_pmu *cci_pmu, int idx)
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@ -266,13 +276,14 @@ static void pmu_set_event(struct cci_pmu *cci_pmu, int idx, unsigned long event)
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pmu_write_register(cci_pmu, event, idx, CCI_PMU_EVT_SEL);
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}
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/*
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* Returns the number of programmable counters actually implemented
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* by the cci
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*/
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static u32 pmu_get_max_counters(void)
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{
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u32 n_cnts = (readl_relaxed(cci_ctrl_base + CCI_PMCR) &
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CCI_PMCR_NCNT_MASK) >> CCI_PMCR_NCNT_SHIFT;
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/* add 1 for cycle counter */
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return n_cnts + 1;
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return (readl_relaxed(cci_ctrl_base + CCI_PMCR) &
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CCI_PMCR_NCNT_MASK) >> CCI_PMCR_NCNT_SHIFT;
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}
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static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *event)
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@ -496,7 +507,7 @@ static void cci_pmu_enable(struct pmu *pmu)
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{
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struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
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struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
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int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_events);
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int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_cntrs);
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unsigned long flags;
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u32 val;
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@ -659,13 +670,16 @@ static int
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validate_group(struct perf_event *event)
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{
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struct perf_event *sibling, *leader = event->group_leader;
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struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
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unsigned long mask[BITS_TO_LONGS(cci_pmu->num_cntrs)];
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struct cci_pmu_hw_events fake_pmu = {
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/*
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* Initialise the fake PMU. We only need to populate the
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* used_mask for the purposes of validation.
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*/
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.used_mask = { 0 },
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.used_mask = mask,
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};
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memset(mask, 0, BITS_TO_LONGS(cci_pmu->num_cntrs) * sizeof(unsigned long));
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if (!validate_event(event->pmu, &fake_pmu, leader))
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return -EINVAL;
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@ -819,6 +833,7 @@ static const struct attribute_group *pmu_attr_groups[] = {
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static int cci_pmu_init(struct cci_pmu *cci_pmu, struct platform_device *pdev)
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{
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char *name = cci_pmu->model->name;
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u32 num_cntrs;
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pmu_cpumask_attr.var = cci_pmu;
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cci_pmu->pmu = (struct pmu) {
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@ -836,7 +851,15 @@ static int cci_pmu_init(struct cci_pmu *cci_pmu, struct platform_device *pdev)
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};
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cci_pmu->plat_device = pdev;
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cci_pmu->num_events = pmu_get_max_counters();
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num_cntrs = pmu_get_max_counters();
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if (num_cntrs > cci_pmu->model->num_hw_cntrs) {
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dev_warn(&pdev->dev,
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"PMU implements more counters(%d) than supported by"
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" the model(%d), truncated.",
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num_cntrs, cci_pmu->model->num_hw_cntrs);
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num_cntrs = cci_pmu->model->num_hw_cntrs;
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}
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cci_pmu->num_cntrs = num_cntrs + cci_pmu->model->fixed_hw_cntrs;
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return perf_pmu_register(&cci_pmu->pmu, name, -1);
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}
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@ -871,6 +894,9 @@ static int cci_pmu_cpu_notifier(struct notifier_block *self,
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static struct cci_pmu_model cci_pmu_models[] = {
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[CCI_REV_R0] = {
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.name = "CCI_400",
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.fixed_hw_cntrs = 1, /* Cycle counter */
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.num_hw_cntrs = 4,
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.cntr_size = SZ_4K,
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.event_ranges = {
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[CCI_IF_SLAVE] = {
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CCI_REV_R0_SLAVE_PORT_MIN_EV,
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@ -884,6 +910,9 @@ static struct cci_pmu_model cci_pmu_models[] = {
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},
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[CCI_REV_R1] = {
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.name = "CCI_400_r1",
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.fixed_hw_cntrs = 1, /* Cycle counter */
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.num_hw_cntrs = 4,
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.cntr_size = SZ_4K,
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.event_ranges = {
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[CCI_IF_SLAVE] = {
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CCI_REV_R1_SLAVE_PORT_MIN_EV,
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@ -938,35 +967,69 @@ static bool is_duplicate_irq(int irq, int *irqs, int nr_irqs)
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return false;
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}
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static struct cci_pmu *cci_pmu_alloc(struct platform_device *pdev)
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{
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struct cci_pmu *cci_pmu;
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const struct cci_pmu_model *model;
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/*
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* All allocations are devm_* hence we don't have to free
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* them explicitly on an error, as it would end up in driver
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* detach.
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*/
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model = get_cci_model(pdev);
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if (!model) {
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dev_warn(&pdev->dev, "CCI PMU version not supported\n");
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return ERR_PTR(-ENODEV);
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}
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cci_pmu = devm_kzalloc(&pdev->dev, sizeof(*cci_pmu), GFP_KERNEL);
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if (!cci_pmu)
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return ERR_PTR(-ENOMEM);
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cci_pmu->model = model;
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cci_pmu->irqs = devm_kcalloc(&pdev->dev, CCI_PMU_MAX_HW_CNTRS(model),
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sizeof(*cci_pmu->irqs), GFP_KERNEL);
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if (!cci_pmu->irqs)
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return ERR_PTR(-ENOMEM);
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cci_pmu->hw_events.events = devm_kcalloc(&pdev->dev,
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CCI_PMU_MAX_HW_CNTRS(model),
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sizeof(*cci_pmu->hw_events.events),
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GFP_KERNEL);
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if (!cci_pmu->hw_events.events)
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return ERR_PTR(-ENOMEM);
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cci_pmu->hw_events.used_mask = devm_kcalloc(&pdev->dev,
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BITS_TO_LONGS(CCI_PMU_MAX_HW_CNTRS(model)),
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sizeof(*cci_pmu->hw_events.used_mask),
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GFP_KERNEL);
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if (!cci_pmu->hw_events.used_mask)
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return ERR_PTR(-ENOMEM);
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return cci_pmu;
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}
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static int cci_pmu_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct cci_pmu *cci_pmu;
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int i, ret, irq;
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const struct cci_pmu_model *model;
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model = get_cci_model(pdev);
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if (!model) {
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dev_warn(&pdev->dev, "CCI PMU version not supported\n");
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return -ENODEV;
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}
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cci_pmu = cci_pmu_alloc(pdev);
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if (IS_ERR(cci_pmu))
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return PTR_ERR(cci_pmu);
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cci_pmu = devm_kzalloc(&pdev->dev, sizeof(*cci_pmu), GFP_KERNEL);
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if (!cci_pmu)
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return -ENOMEM;
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cci_pmu->model = model;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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cci_pmu->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(cci_pmu->base))
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return -ENOMEM;
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/*
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* CCI PMU has 5 overflow signals - one per counter; but some may be tied
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* CCI PMU has one overflow interrupt per counter; but some may be tied
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* together to a common interrupt.
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*/
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cci_pmu->nr_irqs = 0;
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for (i = 0; i < CCI_PMU_MAX_HW_EVENTS; i++) {
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for (i = 0; i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model); i++) {
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irq = platform_get_irq(pdev, i);
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if (irq < 0)
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break;
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@ -981,9 +1044,9 @@ static int cci_pmu_probe(struct platform_device *pdev)
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* Ensure that the device tree has as many interrupts as the number
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* of counters.
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*/
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if (i < CCI_PMU_MAX_HW_EVENTS) {
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if (i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model)) {
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dev_warn(&pdev->dev, "In-correct number of interrupts: %d, should be %d\n",
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i, CCI_PMU_MAX_HW_EVENTS);
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i, CCI_PMU_MAX_HW_CNTRS(cci_pmu->model));
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return -EINVAL;
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}
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