perfcounters/powerpc: add support for POWER5+ processors
Impact: more hardware support This adds the back-end for the PMU on the POWER5+ processors (i.e. GS, including GS DD3 aka POWER5++). This doesn't use the fixed-function PMC5 and PMC6 since they don't respect the freeze conditions and don't generate interrupts, as on POWER6. Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Paul Mackerras
parent
86028598de
commit
aabbaa6036
3 changed files with 458 additions and 2 deletions
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@ -94,8 +94,8 @@ obj-$(CONFIG_AUDIT) += audit.o
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obj64-$(CONFIG_AUDIT) += compat_audit.o
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obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
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obj-$(CONFIG_PERF_COUNTERS) += perf_counter.o ppc970-pmu.o power5-pmu.o \
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power6-pmu.o
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obj-$(CONFIG_PERF_COUNTERS) += perf_counter.o ppc970-pmu.o \
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power5-pmu.o power5+-pmu.o power6-pmu.o
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obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
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@ -826,6 +826,7 @@ void hw_perf_counter_setup(int cpu)
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extern struct power_pmu ppc970_pmu;
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extern struct power_pmu power5_pmu;
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extern struct power_pmu power5p_pmu;
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extern struct power_pmu power6_pmu;
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static int init_perf_counters(void)
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@ -848,6 +849,9 @@ static int init_perf_counters(void)
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case PV_POWER5:
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ppmu = &power5_pmu;
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break;
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case PV_POWER5p:
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ppmu = &power5p_pmu;
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break;
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case 0x3e:
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ppmu = &power6_pmu;
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break;
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452
arch/powerpc/kernel/power5+-pmu.c
Normal file
452
arch/powerpc/kernel/power5+-pmu.c
Normal file
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@ -0,0 +1,452 @@
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/*
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* Performance counter support for POWER5 (not POWER5++) processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/perf_counter.h>
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#include <asm/reg.h>
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/*
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* Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
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*/
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#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
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#define PM_PMC_MSK 0xf
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#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
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#define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */
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#define PM_UNIT_MSK 0xf
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#define PM_BYTE_SH 12 /* Byte number of event bus to use */
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#define PM_BYTE_MSK 7
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#define PM_GRS_SH 8 /* Storage subsystem mux select */
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#define PM_GRS_MSK 7
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#define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */
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#define PM_PMCSEL_MSK 0x7f
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/* Values in PM_UNIT field */
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#define PM_FPU 0
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#define PM_ISU0 1
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#define PM_IFU 2
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#define PM_ISU1 3
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#define PM_IDU 4
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#define PM_ISU0_ALT 6
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#define PM_GRS 7
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#define PM_LSU0 8
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#define PM_LSU1 0xc
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#define PM_LASTUNIT 0xc
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/*
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* Bits in MMCR1 for POWER5+
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*/
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#define MMCR1_TTM0SEL_SH 62
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#define MMCR1_TTM1SEL_SH 60
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#define MMCR1_TTM2SEL_SH 58
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#define MMCR1_TTM3SEL_SH 56
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#define MMCR1_TTMSEL_MSK 3
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#define MMCR1_TD_CP_DBG0SEL_SH 54
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#define MMCR1_TD_CP_DBG1SEL_SH 52
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#define MMCR1_TD_CP_DBG2SEL_SH 50
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#define MMCR1_TD_CP_DBG3SEL_SH 48
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#define MMCR1_GRS_L2SEL_SH 46
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#define MMCR1_GRS_L2SEL_MSK 3
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#define MMCR1_GRS_L3SEL_SH 44
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#define MMCR1_GRS_L3SEL_MSK 3
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#define MMCR1_GRS_MCSEL_SH 41
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#define MMCR1_GRS_MCSEL_MSK 7
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#define MMCR1_GRS_FABSEL_SH 39
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#define MMCR1_GRS_FABSEL_MSK 3
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#define MMCR1_PMC1_ADDER_SEL_SH 35
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#define MMCR1_PMC2_ADDER_SEL_SH 34
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#define MMCR1_PMC3_ADDER_SEL_SH 33
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#define MMCR1_PMC4_ADDER_SEL_SH 32
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#define MMCR1_PMC1SEL_SH 25
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#define MMCR1_PMC2SEL_SH 17
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#define MMCR1_PMC3SEL_SH 9
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#define MMCR1_PMC4SEL_SH 1
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#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
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#define MMCR1_PMCSEL_MSK 0x7f
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/*
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* Bits in MMCRA
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*/
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/*
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* Layout of constraint bits:
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* 6666555555555544444444443333333333222222222211111111110000000000
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* 3210987654321098765432109876543210987654321098765432109876543210
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* [ ><><>< ><> <><>[ > < >< >< >< ><><><><>
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* NC G0G1G2 G3 T0T1 UC B0 B1 B2 B3 P4P3P2P1
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*
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* NC - number of counters
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* 51: NC error 0x0008_0000_0000_0000
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* 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
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*
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* G0..G3 - GRS mux constraints
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* 46-47: GRS_L2SEL value
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* 44-45: GRS_L3SEL value
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* 41-44: GRS_MCSEL value
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* 39-40: GRS_FABSEL value
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* Note that these match up with their bit positions in MMCR1
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*
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* T0 - TTM0 constraint
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* 36-37: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0x30_0000_0000
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*
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* T1 - TTM1 constraint
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* 34-35: TTM1SEL value (0=IDU, 3=GRS) 0x0c_0000_0000
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*
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* UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
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* 33: UC3 error 0x02_0000_0000
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* 32: FPU|IFU|ISU1 events needed 0x01_0000_0000
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* 31: ISU0 events needed 0x01_8000_0000
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* 30: IDU|GRS events needed 0x00_4000_0000
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*
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* B0
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* 20-23: Byte 0 event source 0x00f0_0000
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* Encoding as for the event code
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*
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* B1, B2, B3
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* 16-19, 12-15, 8-11: Byte 1, 2, 3 event sources
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*
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* P4
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* 7: P1 error 0x80
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* 6-7: Count of events needing PMC4
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*
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* P1..P3
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* 0-6: Count of events needing PMC1..PMC3
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*/
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static const int grsel_shift[8] = {
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MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
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MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
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MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
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};
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/* Masks and values for using events from the various units */
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static u64 unit_cons[PM_LASTUNIT+1][2] = {
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[PM_FPU] = { 0x3200000000ull, 0x0100000000ull },
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[PM_ISU0] = { 0x0200000000ull, 0x0080000000ull },
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[PM_ISU1] = { 0x3200000000ull, 0x3100000000ull },
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[PM_IFU] = { 0x3200000000ull, 0x2100000000ull },
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[PM_IDU] = { 0x0e00000000ull, 0x0040000000ull },
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[PM_GRS] = { 0x0e00000000ull, 0x0c40000000ull },
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};
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static int power5p_get_constraint(unsigned int event, u64 *maskp, u64 *valp)
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{
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int pmc, byte, unit, sh;
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int bit, fmask;
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u64 mask = 0, value = 0;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 4)
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return -1;
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sh = (pmc - 1) * 2;
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mask |= 2 << sh;
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value |= 1 << sh;
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}
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if (event & PM_BUSEVENT_MSK) {
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unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
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if (unit > PM_LASTUNIT)
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return -1;
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if (unit == PM_ISU0_ALT)
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unit = PM_ISU0;
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mask |= unit_cons[unit][0];
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value |= unit_cons[unit][1];
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byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
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if (byte >= 4) {
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if (unit != PM_LSU1)
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return -1;
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/* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
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++unit;
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byte &= 3;
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}
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if (unit == PM_GRS) {
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bit = event & 7;
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fmask = (bit == 6)? 7: 3;
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sh = grsel_shift[bit];
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mask |= (u64)fmask << sh;
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value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
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}
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/* Set byte lane select field */
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mask |= 0xfULL << (20 - 4 * byte);
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value |= (u64)unit << (20 - 4 * byte);
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}
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mask |= 0x8000000000000ull;
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value |= 0x1000000000000ull;
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*maskp = mask;
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*valp = value;
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return 0;
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}
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#define MAX_ALT 3 /* at most 3 alternatives for any event */
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ 0x100c0, 0x40001f }, /* PM_GCT_FULL_CYC */
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{ 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */
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{ 0x230e2, 0x323087 }, /* PM_BR_PRED_CR */
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{ 0x230e3, 0x223087, 0x3230a0 }, /* PM_BR_PRED_TA */
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{ 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */
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{ 0x800c4, 0xc20e0 }, /* PM_DTLB_MISS */
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{ 0xc50c6, 0xc60e0 }, /* PM_MRK_DTLB_MISS */
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{ 0x100009, 0x200009 }, /* PM_INST_CMPL */
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{ 0x200015, 0x300015 }, /* PM_LSU_LMQ_SRQ_EMPTY_CYC */
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{ 0x300009, 0x400009 }, /* PM_INST_DISP */
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};
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/*
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* Scan the alternatives table for a match and return the
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* index into the alternatives table if found, else -1.
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*/
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static int find_alternative(unsigned int event)
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{
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int i, j;
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for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
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if (event < event_alternatives[i][0])
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break;
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for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
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if (event == event_alternatives[i][j])
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return i;
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}
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return -1;
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}
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static const unsigned char bytedecode_alternatives[4][4] = {
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/* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
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/* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
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/* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
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/* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
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};
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/*
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* Some direct events for decodes of event bus byte 3 have alternative
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* PMCSEL values on other counters. This returns the alternative
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* event code for those that do, or -1 otherwise. This also handles
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* alternative PCMSEL values for add events.
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*/
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static int find_alternative_bdecode(unsigned int event)
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{
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int pmc, altpmc, pp, j;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc == 0 || pmc > 4)
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return -1;
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altpmc = 5 - pmc; /* 1 <-> 4, 2 <-> 3 */
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pp = event & PM_PMCSEL_MSK;
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for (j = 0; j < 4; ++j) {
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if (bytedecode_alternatives[pmc - 1][j] == pp) {
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return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
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(altpmc << PM_PMC_SH) |
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bytedecode_alternatives[altpmc - 1][j];
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}
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}
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/* new decode alternatives for power5+ */
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if (pmc == 1 && (pp == 0x0d || pp == 0x0e))
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return event + (2 << PM_PMC_SH) + (0x2e - 0x0d);
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if (pmc == 3 && (pp == 0x2e || pp == 0x2f))
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return event - (2 << PM_PMC_SH) - (0x2e - 0x0d);
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/* alternative add event encodings */
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if (pp == 0x10 || pp == 0x28)
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return ((event ^ (0x10 ^ 0x28)) & ~PM_PMC_MSKS) |
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(altpmc << PM_PMC_SH);
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return -1;
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}
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static int power5p_get_alternatives(unsigned int event, unsigned int alt[])
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{
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int i, j, ae, nalt = 1;
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alt[0] = event;
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nalt = 1;
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i = find_alternative(event);
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if (i >= 0) {
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for (j = 0; j < MAX_ALT; ++j) {
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ae = event_alternatives[i][j];
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if (ae && ae != event)
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alt[nalt++] = ae;
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}
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} else {
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ae = find_alternative_bdecode(event);
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if (ae > 0)
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alt[nalt++] = ae;
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}
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return nalt;
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}
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static int power5p_compute_mmcr(unsigned int event[], int n_ev,
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unsigned int hwc[], u64 mmcr[])
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{
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u64 mmcr1 = 0;
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unsigned int pmc, unit, byte, psel;
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unsigned int ttm;
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int i, isbus, bit, grsel;
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unsigned int pmc_inuse = 0;
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unsigned char busbyte[4];
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unsigned char unituse[16];
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int ttmuse;
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if (n_ev > 4)
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return -1;
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/* First pass to count resource use */
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memset(busbyte, 0, sizeof(busbyte));
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memset(unituse, 0, sizeof(unituse));
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 4)
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return -1;
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if (pmc_inuse & (1 << (pmc - 1)))
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return -1;
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pmc_inuse |= 1 << (pmc - 1);
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}
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if (event[i] & PM_BUSEVENT_MSK) {
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unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
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byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
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if (unit > PM_LASTUNIT)
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return -1;
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if (unit == PM_ISU0_ALT)
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unit = PM_ISU0;
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if (byte >= 4) {
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if (unit != PM_LSU1)
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return -1;
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++unit;
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byte &= 3;
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}
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if (busbyte[byte] && busbyte[byte] != unit)
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return -1;
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busbyte[byte] = unit;
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unituse[unit] = 1;
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}
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}
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/*
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* Assign resources and set multiplexer selects.
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*
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* PM_ISU0 can go either on TTM0 or TTM1, but that's the only
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* choice we have to deal with.
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*/
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if (unituse[PM_ISU0] &
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(unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
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unituse[PM_ISU0_ALT] = 1; /* move ISU to TTM1 */
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unituse[PM_ISU0] = 0;
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}
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/* Set TTM[01]SEL fields. */
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ttmuse = 0;
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for (i = PM_FPU; i <= PM_ISU1; ++i) {
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if (!unituse[i])
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continue;
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if (ttmuse++)
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return -1;
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mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
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}
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ttmuse = 0;
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for (; i <= PM_GRS; ++i) {
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if (!unituse[i])
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continue;
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if (ttmuse++)
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return -1;
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mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
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}
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if (ttmuse > 1)
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return -1;
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/* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
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for (byte = 0; byte < 4; ++byte) {
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unit = busbyte[byte];
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if (!unit)
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continue;
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if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
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/* get ISU0 through TTM1 rather than TTM0 */
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unit = PM_ISU0_ALT;
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} else if (unit == PM_LSU1 + 1) {
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/* select lower word of LSU1 for this byte */
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mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
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}
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ttm = unit >> 2;
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mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
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}
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/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
|
||||
for (i = 0; i < n_ev; ++i) {
|
||||
pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
|
||||
unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
|
||||
byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
|
||||
psel = event[i] & PM_PMCSEL_MSK;
|
||||
isbus = event[i] & PM_BUSEVENT_MSK;
|
||||
if (!pmc) {
|
||||
/* Bus event or any-PMC direct event */
|
||||
for (pmc = 0; pmc < 4; ++pmc) {
|
||||
if (!(pmc_inuse & (1 << pmc)))
|
||||
break;
|
||||
}
|
||||
if (pmc >= 4)
|
||||
return -1;
|
||||
pmc_inuse |= 1 << pmc;
|
||||
} else {
|
||||
/* Direct event */
|
||||
--pmc;
|
||||
if (isbus && (byte & 2) &&
|
||||
(psel == 8 || psel == 0x10 || psel == 0x28))
|
||||
/* add events on higher-numbered bus */
|
||||
mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
|
||||
}
|
||||
if (isbus && unit == PM_GRS) {
|
||||
bit = psel & 7;
|
||||
grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
|
||||
mmcr1 |= (u64)grsel << grsel_shift[bit];
|
||||
}
|
||||
if ((psel & 0x58) == 0x40 && (byte & 1) != ((pmc >> 1) & 1))
|
||||
/* select alternate byte lane */
|
||||
psel |= 0x10;
|
||||
if (pmc <= 3)
|
||||
mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
|
||||
hwc[i] = pmc;
|
||||
}
|
||||
|
||||
/* Return MMCRx values */
|
||||
mmcr[0] = 0;
|
||||
if (pmc_inuse & 1)
|
||||
mmcr[0] = MMCR0_PMC1CE;
|
||||
if (pmc_inuse & 0x3e)
|
||||
mmcr[0] |= MMCR0_PMCjCE;
|
||||
mmcr[1] = mmcr1;
|
||||
mmcr[2] = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[])
|
||||
{
|
||||
if (pmc <= 3)
|
||||
mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
|
||||
}
|
||||
|
||||
static int power5p_generic_events[] = {
|
||||
[PERF_COUNT_CPU_CYCLES] = 0xf,
|
||||
[PERF_COUNT_INSTRUCTIONS] = 0x100009,
|
||||
[PERF_COUNT_CACHE_REFERENCES] = 0x1c10a8, /* LD_REF_L1 */
|
||||
[PERF_COUNT_CACHE_MISSES] = 0x3c1088, /* LD_MISS_L1 */
|
||||
[PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x230e4, /* BR_ISSUED */
|
||||
[PERF_COUNT_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
|
||||
};
|
||||
|
||||
struct power_pmu power5p_pmu = {
|
||||
.n_counter = 4,
|
||||
.max_alternatives = MAX_ALT,
|
||||
.add_fields = 0x7000000000055ull,
|
||||
.test_adder = 0x3000040000000ull,
|
||||
.compute_mmcr = power5p_compute_mmcr,
|
||||
.get_constraint = power5p_get_constraint,
|
||||
.get_alternatives = power5p_get_alternatives,
|
||||
.disable_pmc = power5p_disable_pmc,
|
||||
.n_generic = ARRAY_SIZE(power5p_generic_events),
|
||||
.generic_events = power5p_generic_events,
|
||||
};
|
||||
Loading…
Reference in a new issue