clk: renesas: Updates for v4.17 (take two)
- Fix the incorrect display clock on R-Car M3-N, - Always use readl()/writel(), - Small fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJas+E+AAoJEEgEtLw/Ve77zsUP/2pX3Yn/ydkiCzaIhyelGukH /adQ/Bs4jwpltImSBo70qW8p6k6okFaJjy0lunyKRO1rMxu6X9+HMr4Qh2hP/cqz L8QBONxHXOHjiHtpzx7d2SlCGl1TrW5nEAWSJqEuifLIYzxhxxsv1aFkH2wEhLQn P8vgFZMSYeWnMCp/fb0cflmeNuNuGRZQaehUU+9gZQEcPo6pSYohT0ooIvy3OcUA pGB96FtJtUdq0qrZIdHFMv/h2QnZwLBpfFFT1Nl9ATbP/htqxsgH45PZYLqyVgTr F5AtKR/xmMx+P0b+Q8KWAqqfZPtsyPOy/SsBUK49/OeCQsnbZGTWjcRvbSC67y6y VYM+2ve0RSF7oA87+EkKszezNY9H+UJz3G3rzrIaIL+fChshLvjXM5O5YT/oyOxP 4FvxXmcgu1g8qJ3dsXVV6rkR1qsdWKrR4blvqGHB6XHzmeH96mT/znpQUfO6J2rp 9icKL0O9yFMuUe+Lvt7/t+cB16KNOaNrt3/dqgsRfM9Wuch7a1p2XV3MUrreG8FN zd+DJagr4mcHpGS932RMEKqrcpBZUxw+4/VjNxz5GLc90tM11MakaNu9zf0GD3HP GlRcBhckwAX3QgzyH3VrX9KautT4/9XXjMHQFWmjnON2UcZL2LKuGbTahBxpfCc1 PFQ455sXk/jvxFcq2tan =QWlH -----END PGP SIGNATURE----- Merge tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Fix the incorrect display clock on R-Car M3-N, - Always use readl()/writel(), - Small fixes. * tag 'clk-renesas-for-v4.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Adjust r8a77980 ifdef clk: renesas: rcar-gen3: Always use readl()/writel() clk: renesas: sh73a0: Always use readl()/writel() clk: renesas: rza1: Always use readl()/writel() clk: renesas: rcar-gen2: Always use readl()/writel() clk: renesas: r8a7740: Always use readl()/writel() clk: renesas: r8a73a4: Always use readl()/writel() clk: renesas: mstp: Always use readl()/writel() clk: renesas: div6: Always use readl()/writel() clk: renesas: r8a77965: Replace DU2 clock
This commit is contained in:
Stephen Boyd
commit
aa584d28f3
10 changed files with 48 additions and 50 deletions
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@ -53,9 +53,9 @@ static int cpg_div6_clock_enable(struct clk_hw *hw)
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struct div6_clock *clock = to_div6_clock(hw);
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u32 val;
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val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
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val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
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| CPG_DIV6_DIV(clock->div - 1);
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clk_writel(val, clock->reg);
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writel(val, clock->reg);
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return 0;
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}
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@ -65,7 +65,7 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
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struct div6_clock *clock = to_div6_clock(hw);
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u32 val;
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val = clk_readl(clock->reg);
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val = readl(clock->reg);
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val |= CPG_DIV6_CKSTP;
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/*
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* DIV6 clocks require the divisor field to be non-zero when stopping
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@ -75,14 +75,14 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
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*/
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if (!(val & CPG_DIV6_DIV_MASK))
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val |= CPG_DIV6_DIV_MASK;
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clk_writel(val, clock->reg);
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writel(val, clock->reg);
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}
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static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
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return !(readl(clock->reg) & CPG_DIV6_CKSTP);
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}
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static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
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@ -122,10 +122,10 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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clock->div = div;
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val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
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val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
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/* Only program the new divisor if the clock isn't stopped. */
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if (!(val & CPG_DIV6_CKSTP))
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clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
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writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
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return 0;
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}
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@ -139,7 +139,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
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if (clock->src_width == 0)
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return 0;
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hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
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hw_index = (readl(clock->reg) >> clock->src_shift) &
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(BIT(clock->src_width) - 1);
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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if (clock->parents[i] == hw_index)
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@ -163,8 +163,8 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
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mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
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hw_index = clock->parents[index];
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clk_writel((clk_readl(clock->reg) & mask) |
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(hw_index << clock->src_shift), clock->reg);
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writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
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clock->reg);
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return 0;
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}
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@ -241,7 +241,7 @@ struct clk * __init cpg_div6_register(const char *name,
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* Read the divisor. Disabling the clock overwrites the divisor, so we
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* need to cache its value for the enable operation.
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*/
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clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
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clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
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switch (num_parents) {
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case 1:
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@ -64,13 +64,13 @@ struct mstp_clock {
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static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
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u32 __iomem *reg)
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{
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return group->width_8bit ? readb(reg) : clk_readl(reg);
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return group->width_8bit ? readb(reg) : readl(reg);
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}
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static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
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u32 __iomem *reg)
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{
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group->width_8bit ? writeb(val, reg) : clk_writel(val, reg);
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group->width_8bit ? writeb(val, reg) : writel(val, reg);
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}
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static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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@ -71,7 +71,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
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if (!strcmp(name, "main")) {
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u32 ckscr = clk_readl(cpg->reg + CPG_CKSCR);
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u32 ckscr = readl(cpg->reg + CPG_CKSCR);
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switch ((ckscr >> 28) & 3) {
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case 0: /* extal1 */
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@ -95,14 +95,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
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u32 value = readl(cpg->reg + CPG_PLL0CR);
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parent_name = "main";
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mult = ((value >> 24) & 0x7f) + 1;
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if (value & BIT(20))
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div = 2;
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} else if (!strcmp(name, "pll1")) {
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u32 value = clk_readl(cpg->reg + CPG_PLL1CR);
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u32 value = readl(cpg->reg + CPG_PLL1CR);
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parent_name = "main";
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/* XXX: enable bit? */
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@ -125,7 +125,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
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default:
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return ERR_PTR(-EINVAL);
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}
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value = clk_readl(cpg->reg + cr);
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value = readl(cpg->reg + cr);
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switch ((value >> 5) & 7) {
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case 0:
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parent_name = "main";
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@ -161,8 +161,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
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shift = 0;
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}
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div *= 32;
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mult = 0x20 - ((clk_readl(cpg->reg + CPG_FRQCRC) >> shift)
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& 0x1f);
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mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
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} else {
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struct div4_clk *c;
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@ -98,20 +98,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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u32 value = clk_readl(cpg->reg + CPG_FRQCRC);
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u32 value = readl(cpg->reg + CPG_FRQCRC);
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parent_name = "system";
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mult = ((value >> 24) & 0x7f) + 1;
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} else if (!strcmp(name, "pllc1")) {
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u32 value = clk_readl(cpg->reg + CPG_FRQCRA);
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u32 value = readl(cpg->reg + CPG_FRQCRA);
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parent_name = "system";
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mult = ((value >> 24) & 0x7f) + 1;
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div = 2;
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} else if (!strcmp(name, "pllc2")) {
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u32 value = clk_readl(cpg->reg + CPG_PLLC2CR);
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u32 value = readl(cpg->reg + CPG_PLLC2CR);
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parent_name = "system";
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mult = ((value >> 24) & 0x3f) + 1;
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} else if (!strcmp(name, "usb24s")) {
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u32 value = clk_readl(cpg->reg + CPG_USBCKCR);
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u32 value = readl(cpg->reg + CPG_USBCKCR);
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if (value & BIT(7))
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/* extal2 */
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parent_name = of_clk_get_parent_name(np, 1);
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@ -62,8 +62,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
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unsigned int mult;
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unsigned int val;
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val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
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>> CPG_FRQCRC_ZFC_SHIFT;
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val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
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mult = 32 - val;
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return div_u64((u64)parent_rate * mult, 32);
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@ -95,21 +94,21 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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mult = div_u64((u64)rate * 32, parent_rate);
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mult = clamp(mult, 1U, 32U);
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if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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val = clk_readl(zclk->reg);
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val = readl(zclk->reg);
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val &= ~CPG_FRQCRC_ZFC_MASK;
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val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
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clk_writel(val, zclk->reg);
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writel(val, zclk->reg);
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/*
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* Set KICK bit in FRQCRB to update hardware setting and wait for
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* clock change completion.
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*/
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kick = clk_readl(zclk->kick_reg);
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kick = readl(zclk->kick_reg);
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kick |= CPG_FRQCRB_KICK;
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clk_writel(kick, zclk->kick_reg);
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writel(kick, zclk->kick_reg);
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/*
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* Note: There is no HW information about the worst case latency.
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@ -121,7 +120,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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* "super" safe value.
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*/
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for (i = 1000; i; i--) {
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if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
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if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
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return 0;
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cpu_relax();
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@ -332,7 +331,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
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mult = config->pll0_mult;
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div = 3;
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} else {
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u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
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u32 value = readl(cpg->reg + CPG_PLL0CR);
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mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
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}
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parent_name = "main";
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@ -75,9 +75,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
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* let them run at fixed current speed and implement the details later.
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*/
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if (strcmp(name, "i") == 0)
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val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
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val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
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else if (strcmp(name, "g") == 0)
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val = clk_readl(cpg->reg + CPG_FRQCR2) & 3;
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val = readl(cpg->reg + CPG_FRQCR2) & 3;
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else
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return ERR_PTR(-EINVAL);
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@ -85,7 +85,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
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if (!strcmp(name, "main")) {
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/* extal1, extal1_div2, extal2, extal2_div2 */
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u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
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u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
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parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
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div = (parent_idx & 1) + 1;
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@ -110,11 +110,11 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
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default:
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return ERR_PTR(-EINVAL);
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}
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if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
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mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1;
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if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
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mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
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/* handle CFG bit for PLL1 and PLL2 */
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if (enable_bit == 1 || enable_bit == 2)
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if (clk_readl(enable_reg) & BIT(20))
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if (readl(enable_reg) & BIT(20))
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mult *= 2;
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}
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} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
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@ -193,9 +193,9 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
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return;
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/* Set SDHI clocks to a known state */
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clk_writel(0x108, cpg->reg + CPG_SD0CKCR);
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clk_writel(0x108, cpg->reg + CPG_SD1CKCR);
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clk_writel(0x108, cpg->reg + CPG_SD2CKCR);
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writel(0x108, cpg->reg + CPG_SD0CKCR);
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writel(0x108, cpg->reg + CPG_SD1CKCR);
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writel(0x108, cpg->reg + CPG_SD2CKCR);
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for (i = 0; i < num_clks; ++i) {
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const char *name;
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@ -173,7 +173,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
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DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
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DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
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DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
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DEF_MOD("du2", 722, R8A77965_CLK_S2D1),
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DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
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DEF_MOD("du1", 723, R8A77965_CLK_S2D1),
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DEF_MOD("du0", 724, R8A77965_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),
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@ -93,7 +93,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
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unsigned int mult;
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u32 val;
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val = clk_readl(zclk->reg) & zclk->mask;
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val = readl(zclk->reg) & zclk->mask;
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mult = 32 - (val >> __ffs(zclk->mask));
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/* Factor of 2 is for fixed divider */
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@ -125,20 +125,20 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
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mult = clamp(mult, 1U, 32U);
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if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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val = clk_readl(zclk->reg) & ~zclk->mask;
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val = readl(zclk->reg) & ~zclk->mask;
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val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
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clk_writel(val, zclk->reg);
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writel(val, zclk->reg);
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/*
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* Set KICK bit in FRQCRB to update hardware setting and wait for
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* clock change completion.
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*/
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kick = clk_readl(zclk->kick_reg);
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kick = readl(zclk->kick_reg);
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kick |= CPG_FRQCRB_KICK;
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clk_writel(kick, zclk->kick_reg);
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writel(kick, zclk->kick_reg);
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/*
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* Note: There is no HW information about the worst case latency.
|
||||
|
|
@ -150,7 +150,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
* "super" safe value.
|
||||
*/
|
||||
for (i = 1000; i; i--) {
|
||||
if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
|
||||
if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
|
||||
return 0;
|
||||
|
||||
cpu_relax();
|
||||
|
|
|
|||
|
|
@ -705,7 +705,7 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a77970_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_R8A77980
|
||||
#ifdef CONFIG_CLK_R8A77980
|
||||
{
|
||||
.compatible = "renesas,r8a77980-cpg-mssr",
|
||||
.data = &r8a77980_cpg_mssr_info,
|
||||
|
|
|
|||
Loading…
Reference in a new issue