Fixes for system controllers for Atlas/Malta core cards.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
Ralf Baechle
parent
bec0204dfb
commit
aa0980b809
6 changed files with 297 additions and 218 deletions
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@ -1,6 +1,8 @@
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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@ -22,18 +24,17 @@
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/gt64120.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/mips-boards/prom.h>
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#include <asm/mips-boards/generic.h>
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#ifdef CONFIG_MIPS_GT64120
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#include <asm/gt64120.h>
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#endif
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/mips-boards/bonito64.h>
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#ifdef CONFIG_MIPS_MALTA
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/mips-boards/malta.h>
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#endif
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#ifdef CONFIG_KGDB
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extern int rs_kgdb_hook(int, int);
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@ -225,6 +226,8 @@ void __init kgdb_config (void)
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void __init prom_init(void)
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{
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u32 start, map, mask, data;
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prom_argc = fw_arg0;
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_prom_argv = (int *) fw_arg1;
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_prom_envp = (int *) fw_arg2;
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@ -266,12 +269,15 @@ void __init prom_init(void)
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#else
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GT_WRITE(GT_PCI0_CMD_OFS, 0);
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#endif
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/* Fix up PCI I/O mapping if necessary (for Atlas). */
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start = GT_READ(GT_PCI0IOLD_OFS);
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map = GT_READ(GT_PCI0IOREMAP_OFS);
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if ((start & map) != 0) {
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map &= ~start;
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GT_WRITE(GT_PCI0IOREMAP_OFS, map);
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}
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#ifdef CONFIG_MIPS_MALTA
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set_io_port_base(MALTA_GT_PORT_BASE);
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#else
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set_io_port_base((unsigned long)ioremap(0, 0x20000000));
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#endif
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break;
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case MIPS_REVISION_CORID_CORE_EMUL_BON:
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@ -300,11 +306,7 @@ void __init prom_init(void)
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BONITO_BONGENCFG_BYTESWAP;
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#endif
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#ifdef CONFIG_MIPS_MALTA
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set_io_port_base(MALTA_BONITO_PORT_BASE);
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#else
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set_io_port_base((unsigned long)ioremap(0, 0x20000000));
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#endif
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break;
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case MIPS_REVISION_CORID_CORE_MSC:
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@ -312,6 +314,12 @@ void __init prom_init(void)
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
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mb();
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MSC_READ(MSC01_PCI_CFG, data);
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MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
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wmb();
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/* Fix up lane swapping. */
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
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#else
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@ -320,12 +328,23 @@ void __init prom_init(void)
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MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
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MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
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#endif
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/* Fix up target memory mapping. */
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MSC_READ(MSC01_PCI_BAR0, mask);
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MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
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/* Don't handle target retries indefinitely. */
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if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
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MSC01_PCI_CFG_MAXRTRY_MSK)
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data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
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MSC01_PCI_CFG_MAXRTRY_SHF)) |
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((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
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MSC01_PCI_CFG_MAXRTRY_SHF);
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wmb();
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MSC_WRITE(MSC01_PCI_CFG, data);
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mb();
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#ifdef CONFIG_MIPS_MALTA
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set_io_port_base(MALTA_MSC_PORT_BASE);
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#else
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set_io_port_base((unsigned long)ioremap(0, 0x20000000));
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#endif
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break;
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default:
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@ -1,6 +1,8 @@
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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@ -19,65 +21,46 @@
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*
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* MIPS boards specific PCI support.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/gt64120.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/bonito64.h>
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#include <asm/mips-boards/msc01_pci.h>
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#ifdef CONFIG_MIPS_MALTA
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#include <asm/mips-boards/malta.h>
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#endif
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static struct resource bonito64_mem_resource = {
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.name = "Bonito PCI MEM",
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.start = 0x10000000UL,
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.end = 0x1bffffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource bonito64_io_resource = {
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.name = "Bonito IO MEM",
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.start = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */
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.name = "Bonito PCI I/O",
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.start = 0x00000000UL,
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.end = 0x000fffffUL,
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.flags = IORESOURCE_IO,
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};
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static struct resource gt64120_mem_resource = {
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.name = "GT64120 PCI MEM",
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.start = 0x10000000UL,
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.end = 0x1bdfffffUL,
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.name = "GT-64120 PCI MEM",
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.flags = IORESOURCE_MEM,
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};
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static struct resource gt64120_io_resource = {
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.name = "GT64120 IO MEM",
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#ifdef CONFIG_MIPS_ATLAS
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.start = 0x18000000UL,
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.end = 0x181fffffUL,
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#endif
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#ifdef CONFIG_MIPS_MALTA
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.start = 0x00002000UL,
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.end = 0x001fffffUL,
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#endif
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.name = "GT-64120 PCI I/O",
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.flags = IORESOURCE_IO,
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};
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static struct resource msc_mem_resource = {
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.name = "MSC PCI MEM",
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.start = 0x10000000UL,
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.end = 0x1fffffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource msc_io_resource = {
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.name = "MSC IO MEM",
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.start = 0x00002000UL,
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.end = 0x007fffffUL,
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.name = "MSC PCI I/O",
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.flags = IORESOURCE_IO,
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};
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@ -89,7 +72,6 @@ static struct pci_controller bonito64_controller = {
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.pci_ops = &bonito64_pci_ops,
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.io_resource = &bonito64_io_resource,
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.mem_resource = &bonito64_mem_resource,
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.mem_offset = 0x10000000UL,
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.io_offset = 0x00000000UL,
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};
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@ -97,21 +79,18 @@ static struct pci_controller gt64120_controller = {
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.pci_ops = >64120_pci_ops,
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.io_resource = >64120_io_resource,
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.mem_resource = >64120_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_offset = 0x00000000UL,
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};
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static struct pci_controller msc_controller = {
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static struct pci_controller msc_controller = {
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.pci_ops = &msc_pci_ops,
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.io_resource = &msc_io_resource,
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.mem_resource = &msc_mem_resource,
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.mem_offset = 0x10000000UL,
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.io_offset = 0x00000000UL,
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};
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void __init mips_pcibios_init(void)
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{
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struct pci_controller *controller;
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unsigned long start, end, map, start1, end1, map1, map2, map3, mask;
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switch (mips_revision_corid) {
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case MIPS_REVISION_CORID_QED_RM5261:
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@ -130,29 +109,138 @@ void __init mips_pcibios_init(void)
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(0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
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(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
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((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
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GT_PCI0_CFGADDR_CONFIGEN_BIT );
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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/* Perform the write */
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GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
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/* Set up resource ranges from the controller's registers. */
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start = GT_READ(GT_PCI0M0LD_OFS);
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end = GT_READ(GT_PCI0M0HD_OFS);
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map = GT_READ(GT_PCI0M0REMAP_OFS);
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end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
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start1 = GT_READ(GT_PCI0M1LD_OFS);
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end1 = GT_READ(GT_PCI0M1HD_OFS);
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map1 = GT_READ(GT_PCI0M1REMAP_OFS);
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end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
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/* Cannot support multiple windows, use the wider. */
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if (end1 - start1 > end - start) {
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start = start1;
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end = end1;
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map = map1;
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}
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mask = ~(start ^ end);
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/* We don't support remapping with a discontiguous mask. */
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BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
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mask != ~((mask & -mask) - 1));
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gt64120_mem_resource.start = start;
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gt64120_mem_resource.end = end;
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gt64120_controller.mem_offset = (start & mask) - (map & mask);
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/* Addresses are 36-bit, so do shifts in the destinations. */
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gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
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gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
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gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
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gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
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start = GT_READ(GT_PCI0IOLD_OFS);
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end = GT_READ(GT_PCI0IOHD_OFS);
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map = GT_READ(GT_PCI0IOREMAP_OFS);
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end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
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mask = ~(start ^ end);
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/* We don't support remapping with a discontiguous mask. */
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BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
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mask != ~((mask & -mask) - 1));
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gt64120_io_resource.start = map & mask;
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gt64120_io_resource.end = (map & mask) | ~mask;
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gt64120_controller.io_offset = 0;
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/* Addresses are 36-bit, so do shifts in the destinations. */
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gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
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gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
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gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
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controller = >64120_controller;
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break;
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case MIPS_REVISION_CORID_BONITO64:
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case MIPS_REVISION_CORID_CORE_20K:
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case MIPS_REVISION_CORID_CORE_EMUL_BON:
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/* Set up resource ranges from the controller's registers. */
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map = BONITO_PCIMAP;
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map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
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BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
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map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
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BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
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map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
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BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
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/* Combine as many adjacent windows as possible. */
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map = map1;
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start = BONITO_PCILO0_BASE;
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end = 1;
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if (map3 == map2 + 1) {
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map = map2;
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start = BONITO_PCILO1_BASE;
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end++;
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}
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if (map2 == map1 + 1) {
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map = map1;
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start = BONITO_PCILO0_BASE;
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end++;
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}
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bonito64_mem_resource.start = start;
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bonito64_mem_resource.end = start +
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BONITO_PCIMAP_WINBASE(end) - 1;
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bonito64_controller.mem_offset = start -
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BONITO_PCIMAP_WINBASE(map);
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controller = &bonito64_controller;
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break;
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case MIPS_REVISION_CORID_CORE_MSC:
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case MIPS_REVISION_CORID_CORE_FPGA2:
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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/* Set up resource ranges from the controller's registers. */
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MSC_READ(MSC01_PCI_SC2PMBASL, start);
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MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
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MSC_READ(MSC01_PCI_SC2PMMAPL, map);
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msc_mem_resource.start = start & mask;
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msc_mem_resource.end = (start & mask) | ~mask;
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msc_controller.mem_offset = (start & mask) - (map & mask);
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MSC_READ(MSC01_PCI_SC2PIOBASL, start);
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MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
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MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
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msc_io_resource.start = map & mask;
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msc_io_resource.end = (map & mask) | ~mask;
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msc_controller.io_offset = 0;
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ioport_resource.end = ~mask;
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/* If ranges overlap I/O takes precedence. */
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start = start & mask;
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end = start | ~mask;
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if ((start >= msc_mem_resource.start &&
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start <= msc_mem_resource.end) ||
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(end >= msc_mem_resource.start &&
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end <= msc_mem_resource.end)) {
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/* Use the larger space. */
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start = max(start, msc_mem_resource.start);
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end = min(end, msc_mem_resource.end);
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if (start - msc_mem_resource.start >=
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msc_mem_resource.end - end)
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msc_mem_resource.end = start - 1;
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else
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msc_mem_resource.start = end + 1;
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}
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controller = &msc_controller;
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break;
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default:
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return;
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}
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if (controller->io_resource->start < 0x00001000UL) /* FIXME */
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controller->io_resource->start = 0x00001000UL;
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iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
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ioport_resource.end = controller->io_resource->end;
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register_pci_controller (controller);
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@ -1,6 +1,8 @@
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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@ -17,7 +19,6 @@
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*
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* MIPS boards specific PCI support.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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@ -57,13 +58,6 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
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return -1;
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}
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#ifdef CONFIG_MIPS_BOARDS_GEN
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if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
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/* MIPS Core boards have Bonito connected as device 17 */
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return -1;
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}
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#endif
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/* Clear cause register bits */
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BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
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BONITO_PCICMD_MTABORT_CLR);
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@ -1,6 +1,8 @@
|
|||
/*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
|
||||
* Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
|
||||
* All rights reserved.
|
||||
* Authors: Carsten Langgaard <carstenl@mips.com>
|
||||
* Maciej W. Rozycki <macro@mips.com>
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
|
|
@ -43,10 +45,6 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
|
|||
unsigned char busnum = bus->number;
|
||||
u32 intr;
|
||||
|
||||
if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
|
||||
/* Galileo itself is devfn 0, don't move it around */
|
||||
return -1;
|
||||
|
||||
if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
|
||||
return -1; /* Because of a bug in the galileo (for slot 31). */
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
* MIPS boards specific PCI support.
|
||||
*
|
||||
*/
|
||||
#include <linux/config.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -49,34 +48,17 @@ static int msc_pcibios_config_access(unsigned char access_type,
|
|||
struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
|
||||
{
|
||||
unsigned char busnum = bus->number;
|
||||
unsigned char type;
|
||||
u32 intr;
|
||||
|
||||
#ifdef CONFIG_MIPS_BOARDS_GEN
|
||||
if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
|
||||
/* MIPS Core boards have SOCit connected as device 17 */
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clear status register bits. */
|
||||
MSC_WRITE(MSC01_PCI_INTSTAT,
|
||||
(MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
|
||||
|
||||
/* Setup address */
|
||||
if (busnum == 0)
|
||||
type = 0; /* Type 0 */
|
||||
else
|
||||
type = 1; /* Type 1 */
|
||||
|
||||
MSC_WRITE(MSC01_PCI_CFGADDR,
|
||||
((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
|
||||
(PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF)
|
||||
| (PCI_FUNC(devfn) <<
|
||||
MSC01_PCI_CFGADDR_FNUM_SHF) | ((where /
|
||||
4) <<
|
||||
MSC01_PCI_CFGADDR_RNUM_SHF)
|
||||
| (type)));
|
||||
(PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
|
||||
(PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
|
||||
((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
|
||||
|
||||
/* Perform access */
|
||||
if (access_type == PCI_ACCESS_WRITE)
|
||||
|
|
@ -86,15 +68,12 @@ static int msc_pcibios_config_access(unsigned char access_type,
|
|||
|
||||
/* Detect Master/Target abort */
|
||||
MSC_READ(MSC01_PCI_INTSTAT, intr);
|
||||
if (intr & (MSC01_PCI_INTCFG_MA_BIT |
|
||||
MSC01_PCI_INTCFG_TA_BIT)) {
|
||||
if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
|
||||
/* Error occurred */
|
||||
|
||||
/* Clear bits */
|
||||
MSC_READ(MSC01_PCI_INTSTAT, intr);
|
||||
MSC_WRITE(MSC01_PCI_INTSTAT,
|
||||
(MSC01_PCI_INTCFG_MA_BIT |
|
||||
MSC01_PCI_INTCFG_TA_BIT));
|
||||
(MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,8 +1,9 @@
|
|||
/*
|
||||
* PCI Register definitions for the MIPS System Controller.
|
||||
*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
|
||||
* Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved.
|
||||
* Authors: Carsten Langgaard <carstenl@mips.com>
|
||||
* Maciej W. Rozycki <macro@mips.com>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
|
@ -29,22 +30,22 @@
|
|||
#define MSC01_PCI_CFGADDR_OFS 0x0610
|
||||
#define MSC01_PCI_CFGDATA_OFS 0x0618
|
||||
#define MSC01_PCI_IACK_OFS 0x0620
|
||||
#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */
|
||||
#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */
|
||||
#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */
|
||||
#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */
|
||||
#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */
|
||||
#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */
|
||||
#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */
|
||||
#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */
|
||||
#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */
|
||||
#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */
|
||||
#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */
|
||||
#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */
|
||||
#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */
|
||||
#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */
|
||||
#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */
|
||||
#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */
|
||||
#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */
|
||||
#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */
|
||||
#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */
|
||||
#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */
|
||||
#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */
|
||||
#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */
|
||||
#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */
|
||||
#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */
|
||||
#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */
|
||||
#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */
|
||||
#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */
|
||||
#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */
|
||||
#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */
|
||||
#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */
|
||||
#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */
|
||||
#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */
|
||||
#define MSC01_PCI_BAR0_OFS 0x2220
|
||||
#define MSC01_PCI_CFG_OFS 0x2380
|
||||
#define MSC01_PCI_SWAP_OFS 0x2388
|
||||
|
|
@ -86,73 +87,73 @@
|
|||
#define MSC01_PCI_P2SCMAPL_MAP_SHF 24
|
||||
#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000
|
||||
|
||||
#define MSC01_PCI_INTCFG_RST_SHF 10
|
||||
#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
|
||||
#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
|
||||
#define MSC01_PCI_INTCFG_MWE_SHF 9
|
||||
#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
|
||||
#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
|
||||
#define MSC01_PCI_INTCFG_DTO_SHF 8
|
||||
#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
|
||||
#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
|
||||
#define MSC01_PCI_INTCFG_MA_SHF 7
|
||||
#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
|
||||
#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
|
||||
#define MSC01_PCI_INTCFG_TA_SHF 6
|
||||
#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
|
||||
#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
|
||||
#define MSC01_PCI_INTCFG_RTY_SHF 5
|
||||
#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
|
||||
#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
|
||||
#define MSC01_PCI_INTCFG_MWP_SHF 4
|
||||
#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
|
||||
#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
|
||||
#define MSC01_PCI_INTCFG_MRP_SHF 3
|
||||
#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
|
||||
#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
|
||||
#define MSC01_PCI_INTCFG_SWP_SHF 2
|
||||
#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
|
||||
#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
|
||||
#define MSC01_PCI_INTCFG_SRP_SHF 1
|
||||
#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
|
||||
#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
|
||||
#define MSC01_PCI_INTCFG_SE_SHF 0
|
||||
#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
|
||||
#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
|
||||
#define MSC01_PCI_INTCFG_RST_SHF 10
|
||||
#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
|
||||
#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
|
||||
#define MSC01_PCI_INTCFG_MWE_SHF 9
|
||||
#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
|
||||
#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
|
||||
#define MSC01_PCI_INTCFG_DTO_SHF 8
|
||||
#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
|
||||
#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
|
||||
#define MSC01_PCI_INTCFG_MA_SHF 7
|
||||
#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
|
||||
#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
|
||||
#define MSC01_PCI_INTCFG_TA_SHF 6
|
||||
#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
|
||||
#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
|
||||
#define MSC01_PCI_INTCFG_RTY_SHF 5
|
||||
#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
|
||||
#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
|
||||
#define MSC01_PCI_INTCFG_MWP_SHF 4
|
||||
#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
|
||||
#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
|
||||
#define MSC01_PCI_INTCFG_MRP_SHF 3
|
||||
#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
|
||||
#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
|
||||
#define MSC01_PCI_INTCFG_SWP_SHF 2
|
||||
#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
|
||||
#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
|
||||
#define MSC01_PCI_INTCFG_SRP_SHF 1
|
||||
#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
|
||||
#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
|
||||
#define MSC01_PCI_INTCFG_SE_SHF 0
|
||||
#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
|
||||
#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
|
||||
|
||||
#define MSC01_PCI_INTSTAT_RST_SHF 10
|
||||
#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
|
||||
#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
|
||||
#define MSC01_PCI_INTSTAT_MWE_SHF 9
|
||||
#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
|
||||
#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
|
||||
#define MSC01_PCI_INTSTAT_DTO_SHF 8
|
||||
#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
|
||||
#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
|
||||
#define MSC01_PCI_INTSTAT_MA_SHF 7
|
||||
#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
|
||||
#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
|
||||
#define MSC01_PCI_INTSTAT_TA_SHF 6
|
||||
#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
|
||||
#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
|
||||
#define MSC01_PCI_INTSTAT_RTY_SHF 5
|
||||
#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
|
||||
#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
|
||||
#define MSC01_PCI_INTSTAT_MWP_SHF 4
|
||||
#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
|
||||
#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
|
||||
#define MSC01_PCI_INTSTAT_MRP_SHF 3
|
||||
#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
|
||||
#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
|
||||
#define MSC01_PCI_INTSTAT_SWP_SHF 2
|
||||
#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
|
||||
#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
|
||||
#define MSC01_PCI_INTSTAT_SRP_SHF 1
|
||||
#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
|
||||
#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
|
||||
#define MSC01_PCI_INTSTAT_SE_SHF 0
|
||||
#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
|
||||
#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
|
||||
#define MSC01_PCI_INTSTAT_RST_SHF 10
|
||||
#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
|
||||
#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
|
||||
#define MSC01_PCI_INTSTAT_MWE_SHF 9
|
||||
#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
|
||||
#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
|
||||
#define MSC01_PCI_INTSTAT_DTO_SHF 8
|
||||
#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
|
||||
#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
|
||||
#define MSC01_PCI_INTSTAT_MA_SHF 7
|
||||
#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
|
||||
#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
|
||||
#define MSC01_PCI_INTSTAT_TA_SHF 6
|
||||
#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
|
||||
#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
|
||||
#define MSC01_PCI_INTSTAT_RTY_SHF 5
|
||||
#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
|
||||
#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
|
||||
#define MSC01_PCI_INTSTAT_MWP_SHF 4
|
||||
#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
|
||||
#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
|
||||
#define MSC01_PCI_INTSTAT_MRP_SHF 3
|
||||
#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
|
||||
#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
|
||||
#define MSC01_PCI_INTSTAT_SWP_SHF 2
|
||||
#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
|
||||
#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
|
||||
#define MSC01_PCI_INTSTAT_SRP_SHF 1
|
||||
#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
|
||||
#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
|
||||
#define MSC01_PCI_INTSTAT_SE_SHF 0
|
||||
#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
|
||||
#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
|
||||
|
||||
#define MSC01_PCI_CFGADDR_BNUM_SHF 16
|
||||
#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000
|
||||
|
|
@ -167,29 +168,29 @@
|
|||
#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
|
||||
|
||||
/* The defines below are ONLY valid for a MEM bar! */
|
||||
#define MSC01_PCI_BAR0_SIZE_SHF 4
|
||||
#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
|
||||
#define MSC01_PCI_BAR0_P_SHF 3
|
||||
#define MSC01_PCI_BAR0_P_MSK 0x00000008
|
||||
#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
|
||||
#define MSC01_PCI_BAR0_D_SHF 1
|
||||
#define MSC01_PCI_BAR0_D_MSK 0x00000006
|
||||
#define MSC01_PCI_BAR0_T_SHF 0
|
||||
#define MSC01_PCI_BAR0_T_MSK 0x00000001
|
||||
#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
|
||||
#define MSC01_PCI_BAR0_SIZE_SHF 4
|
||||
#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
|
||||
#define MSC01_PCI_BAR0_P_SHF 3
|
||||
#define MSC01_PCI_BAR0_P_MSK 0x00000008
|
||||
#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
|
||||
#define MSC01_PCI_BAR0_D_SHF 1
|
||||
#define MSC01_PCI_BAR0_D_MSK 0x00000006
|
||||
#define MSC01_PCI_BAR0_T_SHF 0
|
||||
#define MSC01_PCI_BAR0_T_MSK 0x00000001
|
||||
#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
|
||||
|
||||
|
||||
#define MSC01_PCI_CFG_RA_SHF 17
|
||||
#define MSC01_PCI_CFG_RA_MSK 0x00020000
|
||||
#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
|
||||
#define MSC01_PCI_CFG_G_SHF 16
|
||||
#define MSC01_PCI_CFG_G_MSK 0x00010000
|
||||
#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
|
||||
#define MSC01_PCI_CFG_EN_SHF 15
|
||||
#define MSC01_PCI_CFG_EN_MSK 0x00008000
|
||||
#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
|
||||
#define MSC01_PCI_CFG_MAXRTRY_SHF 0
|
||||
#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff
|
||||
#define MSC01_PCI_CFG_RA_SHF 17
|
||||
#define MSC01_PCI_CFG_RA_MSK 0x00020000
|
||||
#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
|
||||
#define MSC01_PCI_CFG_G_SHF 16
|
||||
#define MSC01_PCI_CFG_G_MSK 0x00010000
|
||||
#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
|
||||
#define MSC01_PCI_CFG_EN_SHF 15
|
||||
#define MSC01_PCI_CFG_EN_MSK 0x00008000
|
||||
#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
|
||||
#define MSC01_PCI_CFG_MAXRTRY_SHF 0
|
||||
#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff
|
||||
|
||||
#define MSC01_PCI_SWAP_IO_SHF 18
|
||||
#define MSC01_PCI_SWAP_IO_MSK 0x000c0000
|
||||
|
|
@ -206,7 +207,7 @@
|
|||
* FIXME - are these macros specific to Malta and co or to the MSC? If the
|
||||
* latter, they should be moved elsewhere.
|
||||
*/
|
||||
#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
|
||||
#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
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extern unsigned long _pcictrl_msc;
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@ -219,19 +220,19 @@ extern unsigned long _pcictrl_msc;
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* Registers absolute addresses
|
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*/
|
||||
|
||||
#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
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||||
#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
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||||
#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
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#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
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#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
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#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
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||||
#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
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#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
|
||||
#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
|
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#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
|
||||
#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
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#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
|
||||
#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
|
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#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
|
||||
#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
|
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#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
|
||||
#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
|
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#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
|
||||
#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
|
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#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
|
||||
#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
|
||||
#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
|
||||
#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
|
||||
#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
|
||||
#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
|
||||
#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
|
||||
#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
|
||||
#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
|
||||
#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
|
||||
|
|
@ -248,7 +249,7 @@ extern unsigned long _pcictrl_msc;
|
|||
#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
|
||||
#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
|
||||
#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
|
||||
#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
|
||||
#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
|
||||
#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
|
||||
#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
|
||||
#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
|
||||
|
|
|
|||
Loading…
Reference in a new issue