ARM: imx6q: remove board specific CLKO setup
The CLKO is widely used by imx6q board designs to clock audio codec. Since most codecs accept 24 MHz frequency, let's initially set up CLKO with OSC24M (cko <-- cko2 <-- osc). Then those board specific CLKO setup for audio codec can be removed. The board dts files also need an update on cko reference in codec node. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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5da826abe9
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5 changed files with 14 additions and 72 deletions
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@ -167,7 +167,7 @@
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clocks = <&clks 169>;
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clocks = <&clks 201>;
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VDDA-supply = <®_2p5v>;
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VDDIO-supply = <®_3p3v>;
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};
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@ -109,7 +109,7 @@
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codec: wm8962@1a {
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compatible = "wlf,wm8962";
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reg = <0x1a>;
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clocks = <&clks 169>;
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clocks = <&clks 201>;
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DCVDD-supply = <®_audio>;
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DBVDD-supply = <®_audio>;
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AVDD-supply = <®_audio>;
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@ -60,7 +60,7 @@
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codec: sgtl5000@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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clocks = <&clks 169>;
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clocks = <&clks 201>;
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VDDA-supply = <®_2p5v>;
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VDDIO-supply = <®_3p3v>;
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};
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@ -288,6 +288,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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struct device_node *np;
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void __iomem *base;
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int i, irq;
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int ret;
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clk[dummy] = imx_clk_fixed("dummy", 0);
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clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
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@ -592,6 +593,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk_prepare_enable(clk[usbphy2_gate]);
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}
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/*
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* Let's initially set up CLKO with OSC24M, since this configuration
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* is widely used by imx6q board designs to clock audio codec.
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*/
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ret = clk_set_parent(clk[cko2_sel], clk[osc]);
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if (!ret)
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ret = clk_set_parent(clk[cko], clk[cko2]);
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if (ret)
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pr_warn("failed to set up CLKO: %d\n", ret);
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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@ -162,30 +162,6 @@ static int ar8031_phy_fixup(struct phy_device *dev)
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return 0;
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}
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static void __init imx6q_sabrelite_cko1_setup(void)
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{
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struct clk *cko1_sel, *ahb, *cko1;
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unsigned long rate;
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cko1_sel = clk_get_sys(NULL, "cko1_sel");
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ahb = clk_get_sys(NULL, "ahb");
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cko1 = clk_get_sys(NULL, "cko1");
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if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
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pr_err("cko1 setup failed!\n");
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goto put_clk;
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}
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clk_set_parent(cko1_sel, ahb);
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rate = clk_round_rate(cko1, 16000000);
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clk_set_rate(cko1, rate);
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put_clk:
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if (!IS_ERR(cko1_sel))
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clk_put(cko1_sel);
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if (!IS_ERR(ahb))
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clk_put(ahb);
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if (!IS_ERR(cko1))
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clk_put(cko1);
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}
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#define PHY_ID_AR8031 0x004dd074
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static void __init imx6q_enet_phy_init(void)
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@ -200,45 +176,6 @@ static void __init imx6q_enet_phy_init(void)
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}
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}
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static void __init imx6q_sabresd_cko1_setup(void)
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{
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struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
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unsigned long rate;
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cko1_sel = clk_get_sys(NULL, "cko1_sel");
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pll4 = clk_get_sys(NULL, "pll4_audio");
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pll4_post = clk_get_sys(NULL, "pll4_post_div");
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cko1 = clk_get_sys(NULL, "cko1");
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if (IS_ERR(cko1_sel) || IS_ERR(pll4)
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|| IS_ERR(pll4_post) || IS_ERR(cko1)) {
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pr_err("cko1 setup failed!\n");
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goto put_clk;
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}
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/*
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* Setting pll4 at 768MHz (24MHz * 32)
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* So its child clock can get 24MHz easily
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*/
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clk_set_rate(pll4, 768000000);
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clk_set_parent(cko1_sel, pll4_post);
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rate = clk_round_rate(cko1, 24000000);
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clk_set_rate(cko1, rate);
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put_clk:
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if (!IS_ERR(cko1_sel))
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clk_put(cko1_sel);
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if (!IS_ERR(pll4_post))
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clk_put(pll4_post);
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if (!IS_ERR(pll4))
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clk_put(pll4);
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if (!IS_ERR(cko1))
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clk_put(cko1);
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}
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static void __init imx6q_sabresd_init(void)
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{
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imx6q_sabresd_cko1_setup();
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}
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static void __init imx6q_1588_init(void)
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{
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struct regmap *gpr;
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@ -255,12 +192,6 @@ static void __init imx6q_1588_init(void)
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static void __init imx6q_init_machine(void)
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{
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if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
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imx6q_sabrelite_cko1_setup();
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else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
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of_machine_is_compatible("fsl,imx6dl-sabresd"))
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imx6q_sabresd_init();
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imx6q_enet_phy_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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