x86: Move the 64-bit Intel specific parts out of setup_64.c
Create a separate intel_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Dave Jones
H. Peter Anvin
parent
4d28587856
commit
a82fbe31cb
3 changed files with 100 additions and 91 deletions
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@ -12,6 +12,7 @@ obj-$(CONFIG_X86_32) += cyrix.o
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obj-$(CONFIG_X86_32) += centaur.o
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obj-$(CONFIG_X86_32) += transmeta.o
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obj-$(CONFIG_X86_32) += intel.o
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obj-$(CONFIG_X86_64) += intel_64.o
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obj-$(CONFIG_X86_32) += umc.o
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obj-$(CONFIG_X86_MCE) += mcheck/
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97
arch/x86/kernel/cpu/intel_64.c
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97
arch/x86/kernel/cpu/intel_64.c
Normal file
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@ -0,0 +1,97 @@
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/topology.h>
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#include <asm/numa_64.h>
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void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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{
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if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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(c->x86 == 0x6 && c->x86_model >= 0x0e))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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}
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/*
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* find out the number of processor cores on the die
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*/
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static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
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{
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unsigned int eax, t;
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if (c->cpuid_level < 4)
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return 1;
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cpuid_count(4, 0, &eax, &t, &t, &t);
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if (eax & 0x1f)
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return ((eax >> 26) + 1);
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else
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return 1;
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}
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static void __cpuinit srat_detect_node(void)
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{
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#ifdef CONFIG_NUMA
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unsigned node;
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int cpu = smp_processor_id();
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int apicid = hard_smp_processor_id();
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/* Don't do the funky fallback heuristics the AMD version employs
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for now. */
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node = apicid_to_node[apicid];
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if (node == NUMA_NO_NODE || !node_online(node))
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node = first_node(node_online_map);
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numa_set_node(cpu, node);
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printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
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#endif
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}
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void __cpuinit init_intel(struct cpuinfo_x86 *c)
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{
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/* Cache sizes */
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unsigned n;
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init_intel_cacheinfo(c);
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if (c->cpuid_level > 9) {
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unsigned eax = cpuid_eax(10);
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/* Check for version and the number of counters */
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if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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if (cpu_has_ds) {
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unsigned int l1, l2;
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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if (!(l1 & (1<<11)))
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set_cpu_cap(c, X86_FEATURE_BTS);
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if (!(l1 & (1<<12)))
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set_cpu_cap(c, X86_FEATURE_PEBS);
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}
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if (cpu_has_bts)
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ds_init_intel(c);
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n = c->extended_cpuid_level;
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if (n >= 0x80000008) {
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unsigned eax = cpuid_eax(0x80000008);
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c->x86_virt_bits = (eax >> 8) & 0xff;
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c->x86_phys_bits = eax & 0xff;
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/* CPUID workaround for Intel 0F34 CPU */
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if (c->x86_vendor == X86_VENDOR_INTEL &&
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c->x86 == 0xF && c->x86_model == 0x3 &&
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c->x86_mask == 0x4)
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c->x86_phys_bits = 36;
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}
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if (c->x86 == 15)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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c->x86_max_cores = intel_num_cpu_cores(c);
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srat_detect_node();
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}
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@ -622,97 +622,6 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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#endif
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}
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/*
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* find out the number of processor cores on the die
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*/
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static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
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{
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unsigned int eax, t;
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if (c->cpuid_level < 4)
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return 1;
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cpuid_count(4, 0, &eax, &t, &t, &t);
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if (eax & 0x1f)
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return ((eax >> 26) + 1);
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else
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return 1;
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}
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static void __cpuinit srat_detect_node(void)
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{
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#ifdef CONFIG_NUMA
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unsigned node;
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int cpu = smp_processor_id();
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int apicid = hard_smp_processor_id();
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/* Don't do the funky fallback heuristics the AMD version employs
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for now. */
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node = apicid_to_node[apicid];
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if (node == NUMA_NO_NODE || !node_online(node))
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node = first_node(node_online_map);
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numa_set_node(cpu, node);
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printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
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#endif
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}
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static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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{
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if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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(c->x86 == 0x6 && c->x86_model >= 0x0e))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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}
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static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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{
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/* Cache sizes */
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unsigned n;
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init_intel_cacheinfo(c);
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if (c->cpuid_level > 9) {
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unsigned eax = cpuid_eax(10);
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/* Check for version and the number of counters */
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if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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if (cpu_has_ds) {
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unsigned int l1, l2;
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rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
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if (!(l1 & (1<<11)))
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set_cpu_cap(c, X86_FEATURE_BTS);
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if (!(l1 & (1<<12)))
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set_cpu_cap(c, X86_FEATURE_PEBS);
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}
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if (cpu_has_bts)
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ds_init_intel(c);
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n = c->extended_cpuid_level;
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if (n >= 0x80000008) {
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unsigned eax = cpuid_eax(0x80000008);
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c->x86_virt_bits = (eax >> 8) & 0xff;
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c->x86_phys_bits = eax & 0xff;
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/* CPUID workaround for Intel 0F34 CPU */
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if (c->x86_vendor == X86_VENDOR_INTEL &&
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c->x86 == 0xF && c->x86_model == 0x3 &&
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c->x86_mask == 0x4)
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c->x86_phys_bits = 36;
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}
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if (c->x86 == 15)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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c->x86_max_cores = intel_num_cpu_cores(c);
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srat_detect_node();
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}
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static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
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{
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if (c->x86 == 0x6 && c->x86_model >= 0xf)
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@ -756,6 +665,8 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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// FIXME: Needs to use cpu_vendor_dev_register
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extern void __cpuinit early_init_amd(struct cpuinfo_x86 *c);
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extern void __cpuinit init_amd(struct cpuinfo_x86 *c);
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extern void __cpuinit early_init_intel(struct cpuinfo_x86 *c);
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extern void __cpuinit init_intel(struct cpuinfo_x86 *c);
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/* Do some early cpuid on the boot CPU to get some parameter that are
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needed before check_bugs. Everything advanced is in identify_cpu
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