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ARM: at91: add ram controller DT support

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We can now drop the call to ioremap_registers() as we have the binding for the
SDRAM/DDR Controller.

Drop ioremap_registers() for sam9x5 too.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2012-03-02 20:54:37 +08:00
parent c8082d344a
commit a7776ec625
8 changed files with 72 additions and 27 deletions
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19
Documentation/devicetree/bindings/arm/atmel-at91.txt
View file

@ -42,3 +42,22 @@ Example:
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
};
RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
- reg: Should contain registers location and length
For at91sam9263 and at91sam9g45 you must specify 2 entries.
Examples:
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
};
ramc0: ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe400 0x200
0xffffe600 0x200>;
};

5
arch/arm/boot/dts/at91sam9g20.dtsi
View file

@ -59,6 +59,11 @@
reg = <0xfffff000 0x200>;
};
ramc0: ramc@ffffea00 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffea00 0x200>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;

6
arch/arm/boot/dts/at91sam9g45.dtsi
View file

@ -60,6 +60,12 @@
reg = <0xfffff000 0x200>;
};
ramc0: ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe400 0x200
0xffffe600 0x200>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;

5
arch/arm/boot/dts/at91sam9x5.dtsi
View file

@ -58,6 +58,11 @@
reg = <0xfffff000 0x200>;
};
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;

6
arch/arm/mach-at91/at91sam9x5.c
View file

@ -299,11 +299,6 @@ static void __init at91sam9x5_map_io(void)
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
}
static void __init at91sam9x5_ioremap_registers(void)
{
at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
}
void __init at91sam9x5_initialize(void)
{
at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
@ -356,7 +351,6 @@ static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
struct at91_init_soc __initdata at91sam9x5_soc = {
.map_io = at91sam9x5_map_io,
.default_irq_priority = at91sam9x5_default_irq_priority,
.ioremap_registers = at91sam9x5_ioremap_registers,
.register_clocks = at91sam9x5_register_clocks,
.init = at91sam9x5_initialize,
};

5
arch/arm/mach-at91/include/mach/at91sam9x5.h
View file

@ -54,11 +54,6 @@
#define AT91SAM9X5_BASE_USART1 0xf8020000
#define AT91SAM9X5_BASE_USART2 0xf8024000
/*
* System Peripherals
*/
#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
/*
* Base addresses for early serial code (uncompress.h)
*/

13
arch/arm/mach-at91/pm.c
View file

@ -197,19 +197,6 @@ extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
extern u32 at91_slow_clock_sz;
#endif
void __iomem *at91_ramc_base[2];
void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
{
if (id < 0 || id > 1) {
pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
BUG();
}
at91_ramc_base[id] = ioremap(addr, size);
if (!at91_ramc_base[id])
panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
}
static int at91_pm_enter(suspend_state_t state)
{
at91_gpio_suspend();

40
arch/arm/mach-at91/setup.c
View file

@ -52,6 +52,19 @@ void __init at91_init_interrupts(unsigned int *priority)
at91_gpio_irq_setup();
}
void __iomem *at91_ramc_base[2];
void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
{
if (id < 0 || id > 1) {
pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
BUG();
}
at91_ramc_base[id] = ioremap(addr, size);
if (!at91_ramc_base[id])
panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
}
static struct map_desc sram_desc[2] __initdata;
void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
@ -315,12 +328,33 @@ static void at91_dt_rstc(void)
of_node_put(np);
}
static struct of_device_id ramc_ids[] = {
{ .compatible = "atmel,at91sam9260-sdramc" },
{ .compatible = "atmel,at91sam9g45-ddramc" },
{ /*sentinel*/ }
};
static void at91_dt_ramc(void)
{
struct device_node *np;
np = of_find_matching_node(NULL, ramc_ids);
if (!np)
panic("unable to find compatible ram conroller node in dtb\n");
at91_ramc_base[0] = of_iomap(np, 0);
if (!at91_ramc_base[0])
panic("unable to map ramc[0] cpu registers\n");
/* the controller may have 2 banks */
at91_ramc_base[1] = of_iomap(np, 1);
of_node_put(np);
}
void __init at91_dt_initialize(void)
{
at91_dt_rstc();
/* temporary until have the ramc binding*/
at91_boot_soc.ioremap_registers();
at91_dt_ramc();
/* Init clock subsystem */
at91_dt_clock_init();