xtensa: enable HAVE_PERF_EVENTS

This allows the perf tool to monitor kernel tracepoint events.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Baruch Siach 2013-11-28 18:00:04 +02:00 committed by Max Filippov
parent 6cb971114f
commit a6f3eefad8
2 changed files with 5 additions and 0 deletions

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@ -19,6 +19,7 @@ config XTENSA
select HAVE_OPROFILE select HAVE_OPROFILE
select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_TRACER
select HAVE_IRQ_TIME_ACCOUNTING select HAVE_IRQ_TIME_ACCOUNTING
select HAVE_PERF_EVENTS
help help
Xtensa processors are 32-bit RISC machines designed by Tensilica Xtensa processors are 32-bit RISC machines designed by Tensilica
primarily for embedded systems. These processors are both primarily for embedded systems. These processors are both

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@ -0,0 +1,4 @@
#ifndef __ASM_XTENSA_PERF_EVENT_H
#define __ASM_XTENSA_PERF_EVENT_H
#endif /* __ASM_XTENSA_PERF_EVENT_H */