irqchip/irq-mvebu-gicp: Add new driver for Marvell GICP
This commit adds a simple driver for the Marvell GICP, a hardware unit that converts memory writes into GIC SPI interrupts. The driver provides a number of functions to the ICU driver to allocate GICP interrupts, and get the physical addresses that the ICUs should write to to set/clear interrupts. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Thomas Petazzoni
Marc Zyngier
parent
f39a29bb5c
commit
a68a63cb4d
4 changed files with 294 additions and 0 deletions
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@ -268,6 +268,9 @@ config IRQ_MXS
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select IRQ_DOMAIN
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select STMP_DEVICE
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config MVEBU_GICP
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bool
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config MVEBU_ODMI
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
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obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
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obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
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obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
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obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
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obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
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obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
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obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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279
drivers/irqchip/irq-mvebu-gicp.c
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279
drivers/irqchip/irq-mvebu-gicp.c
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@ -0,0 +1,279 @@
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/*
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* Copyright (C) 2017 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "irq-mvebu-gicp.h"
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#define GICP_SETSPI_NSR_OFFSET 0x0
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#define GICP_CLRSPI_NSR_OFFSET 0x8
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struct mvebu_gicp_spi_range {
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unsigned int start;
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unsigned int count;
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};
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struct mvebu_gicp {
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struct mvebu_gicp_spi_range *spi_ranges;
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unsigned int spi_ranges_cnt;
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unsigned int spi_cnt;
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unsigned long *spi_bitmap;
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spinlock_t spi_lock;
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struct resource *res;
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struct device *dev;
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};
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static int gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx)
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{
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int i;
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for (i = 0; i < gicp->spi_ranges_cnt; i++) {
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struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
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if (idx < r->count)
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return r->start + idx;
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idx -= r->count;
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}
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return -EINVAL;
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}
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int mvebu_gicp_get_doorbells(struct device_node *dn, phys_addr_t *setspi,
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phys_addr_t *clrspi)
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{
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struct platform_device *pdev;
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struct mvebu_gicp *gicp;
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pdev = of_find_device_by_node(dn);
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if (!pdev)
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return -ENODEV;
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gicp = platform_get_drvdata(pdev);
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if (!gicp)
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return -ENODEV;
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*setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
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*clrspi = gicp->res->start + GICP_CLRSPI_NSR_OFFSET;
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return 0;
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}
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static void gicp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct mvebu_gicp *gicp = data->chip_data;
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phys_addr_t setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
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msg->data = data->hwirq;
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msg->address_lo = lower_32_bits(setspi);
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msg->address_hi = upper_32_bits(setspi);
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}
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static struct irq_chip gicp_irq_chip = {
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.name = "GICP",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_type = irq_chip_set_type_parent,
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.irq_compose_msi_msg = gicp_compose_msi_msg,
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};
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static int gicp_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct mvebu_gicp *gicp = domain->host_data;
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struct irq_fwspec fwspec;
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unsigned int hwirq;
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int ret;
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spin_lock(&gicp->spi_lock);
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hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
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if (hwirq == gicp->spi_cnt) {
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spin_unlock(&gicp->spi_lock);
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return -ENOSPC;
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}
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__set_bit(hwirq, gicp->spi_bitmap);
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spin_unlock(&gicp->spi_lock);
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fwspec.fwnode = domain->parent->fwnode;
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fwspec.param_count = 3;
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fwspec.param[0] = GIC_SPI;
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fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32;
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/*
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* Assume edge rising for now, it will be properly set when
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* ->set_type() is called
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*/
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fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
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ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
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if (ret) {
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dev_err(gicp->dev, "Cannot allocate parent IRQ\n");
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goto free_hwirq;
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}
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&gicp_irq_chip, gicp);
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if (ret)
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goto free_irqs_parent;
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return 0;
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free_irqs_parent:
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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free_hwirq:
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spin_lock(&gicp->spi_lock);
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__clear_bit(hwirq, gicp->spi_bitmap);
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spin_unlock(&gicp->spi_lock);
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return ret;
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}
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static void gicp_irq_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct mvebu_gicp *gicp = domain->host_data;
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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if (d->hwirq >= gicp->spi_cnt) {
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dev_err(gicp->dev, "Invalid hwirq %lu\n", d->hwirq);
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return;
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}
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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spin_lock(&gicp->spi_lock);
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__clear_bit(d->hwirq, gicp->spi_bitmap);
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spin_unlock(&gicp->spi_lock);
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}
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static const struct irq_domain_ops gicp_domain_ops = {
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.alloc = gicp_irq_domain_alloc,
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.free = gicp_irq_domain_free,
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};
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static struct irq_chip gicp_msi_irq_chip = {
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.name = "GICP",
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.irq_set_type = irq_chip_set_type_parent,
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};
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static struct msi_domain_ops gicp_msi_ops = {
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};
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static struct msi_domain_info gicp_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
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.ops = &gicp_msi_ops,
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.chip = &gicp_msi_irq_chip,
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};
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static int mvebu_gicp_probe(struct platform_device *pdev)
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{
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struct mvebu_gicp *gicp;
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struct irq_domain *inner_domain, *plat_domain, *parent_domain;
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struct device_node *node = pdev->dev.of_node;
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struct device_node *irq_parent_dn;
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int ret, i;
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gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL);
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if (!gicp)
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return -ENOMEM;
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gicp->dev = &pdev->dev;
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gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!gicp->res)
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return -ENODEV;
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ret = of_property_count_u32_elems(node, "marvell,spi-ranges");
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if (ret < 0)
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return ret;
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gicp->spi_ranges_cnt = ret / 2;
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gicp->spi_ranges =
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devm_kzalloc(&pdev->dev,
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gicp->spi_ranges_cnt *
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sizeof(struct mvebu_gicp_spi_range),
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GFP_KERNEL);
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if (!gicp->spi_ranges)
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return -ENOMEM;
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for (i = 0; i < gicp->spi_ranges_cnt; i++) {
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of_property_read_u32_index(node, "marvell,spi-ranges",
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i * 2,
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&gicp->spi_ranges[i].start);
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of_property_read_u32_index(node, "marvell,spi-ranges",
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i * 2 + 1,
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&gicp->spi_ranges[i].count);
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gicp->spi_cnt += gicp->spi_ranges[i].count;
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}
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gicp->spi_bitmap = devm_kzalloc(&pdev->dev,
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BITS_TO_LONGS(gicp->spi_cnt),
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GFP_KERNEL);
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if (!gicp->spi_bitmap)
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return -ENOMEM;
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irq_parent_dn = of_irq_find_parent(node);
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if (!irq_parent_dn) {
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dev_err(&pdev->dev, "failed to find parent IRQ node\n");
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return -ENODEV;
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}
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parent_domain = irq_find_host(irq_parent_dn);
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if (!parent_domain) {
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dev_err(&pdev->dev, "failed to find parent IRQ domain\n");
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return -ENODEV;
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}
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inner_domain = irq_domain_create_hierarchy(parent_domain, 0,
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gicp->spi_cnt,
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of_node_to_fwnode(node),
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&gicp_domain_ops, gicp);
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if (!inner_domain)
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return -ENOMEM;
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plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
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&gicp_msi_domain_info,
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inner_domain);
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if (!plat_domain) {
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irq_domain_remove(inner_domain);
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, gicp);
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return 0;
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}
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static const struct of_device_id mvebu_gicp_of_match[] = {
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{ .compatible = "marvell,ap806-gicp", },
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{},
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};
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static struct platform_driver mvebu_gicp_driver = {
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.probe = mvebu_gicp_probe,
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.driver = {
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.name = "mvebu-gicp",
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.of_match_table = mvebu_gicp_of_match,
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},
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};
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builtin_platform_driver(mvebu_gicp_driver);
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11
drivers/irqchip/irq-mvebu-gicp.h
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11
drivers/irqchip/irq-mvebu-gicp.h
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@ -0,0 +1,11 @@
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#ifndef __MVEBU_GICP_H__
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#define __MVEBU_GICP_H__
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#include <linux/types.h>
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struct device_node;
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int mvebu_gicp_get_doorbells(struct device_node *dn, phys_addr_t *setspi,
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phys_addr_t *clrspi);
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#endif /* __MVEBU_GICP_H__ */
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