ARM: OMAP2+: Add clock domain support for dm816x
This patch adds required definitions and structures for clockdomain initialization, so omap3xxx_clockdomains_init() was substituted by new ti81xx_clockdomains_init() while early initialization of TI81XX platform. Note that we now need to have 81xx in a separate CONFIG_SOC_TI81XX block instead inside the ifdef block for omap3 to avoid make randconfig build errors. This code is based on the TI81XX-LINUX-PSP-04.04.00.02 patches published at: http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru> [tony@atomide.com: updated to apply, renamed to clockdomains81xx.c, fixed to use am33xx_clkdm_operations, various fixes suggested by Paul Walmsley] Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Aida Mynzhasova
Tony Lindgren
parent
abf8cc1d5b
commit
a64459c42d
5 changed files with 298 additions and 38 deletions
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@ -171,6 +171,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
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obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
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obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
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obj-$(CONFIG_SOC_TI81XX) += $(clockdomain-common)
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obj-$(CONFIG_SOC_TI81XX) += clockdomains81xx_data.o
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obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
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obj-$(CONFIG_SOC_AM43XX) += clockdomains43xx_data.o
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obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
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@ -216,6 +216,7 @@ extern void __init omap242x_clockdomains_init(void);
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extern void __init omap243x_clockdomains_init(void);
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extern void __init omap3xxx_clockdomains_init(void);
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extern void __init am33xx_clockdomains_init(void);
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extern void __init ti81xx_clockdomains_init(void);
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extern void __init omap44xx_clockdomains_init(void);
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extern void __init omap54xx_clockdomains_init(void);
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extern void __init dra7xx_clockdomains_init(void);
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194
arch/arm/mach-omap2/clockdomains81xx_data.c
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194
arch/arm/mach-omap2/clockdomains81xx_data.c
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@ -0,0 +1,194 @@
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/*
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* TI81XX Clock Domain data.
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*
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* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
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* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "cm81xx.h"
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/*
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* Note that 814x seems to have HWSUP_SWSUP for many clockdomains
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* while 816x does not. According to the TRM, 816x only has HWSUP
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* for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h
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* seems to have the related ifdef the wrong way around claiming
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* 816x supports HWSUP while 814x does not. For now, we only set
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* HWSUP for ALWON_L3_FAST as that seems to be supported for both
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* dm814x and dm816x.
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*/
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/* Common for 81xx */
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static struct clockdomain alwon_l3_slow_81xx_clkdm = {
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.name = "alwon_l3s_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain alwon_l3_med_81xx_clkdm = {
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.name = "alwon_l3_med_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain alwon_l3_fast_81xx_clkdm = {
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.name = "alwon_l3_fast_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain alwon_ethernet_81xx_clkdm = {
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.name = "alwon_ethernet_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ETHERNET_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mmu_81xx_clkdm = {
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.name = "mmu_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_MMU_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain mmu_cfg_81xx_clkdm = {
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.name = "mmu_cfg_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_MMUCFG_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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/* 816x only */
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static struct clockdomain alwon_mpu_816x_clkdm = {
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.name = "alwon_mpu_clkdm",
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.pwrdm = { .name = "alwon_pwrdm" },
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.cm_inst = TI81XX_CM_ALWON_MOD,
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.clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain active_gem_816x_clkdm = {
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.name = "active_gem_clkdm",
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.pwrdm = { .name = "active_pwrdm" },
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.cm_inst = TI816X_CM_ACTIVE_MOD,
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.clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd0_816x_clkdm = {
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.name = "ivahd0_clkdm",
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.pwrdm = { .name = "ivahd0_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD0_MOD,
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.clkdm_offs = TI816X_CM_IVAHD0_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd1_816x_clkdm = {
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.name = "ivahd1_clkdm",
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.pwrdm = { .name = "ivahd1_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD1_MOD,
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.clkdm_offs = TI816X_CM_IVAHD1_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain ivahd2_816x_clkdm = {
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.name = "ivahd2_clkdm",
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.pwrdm = { .name = "ivahd2_pwrdm" },
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.cm_inst = TI816X_CM_IVAHD2_MOD,
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.clkdm_offs = TI816X_CM_IVAHD2_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain sgx_816x_clkdm = {
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.name = "sgx_clkdm",
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.pwrdm = { .name = "sgx_pwrdm" },
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.cm_inst = TI816X_CM_SGX_MOD,
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.clkdm_offs = TI816X_CM_SGX_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_l3_med_816x_clkdm = {
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.name = "default_l3_med_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI816X_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_ducati_816x_clkdm = {
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.name = "default_ducati_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI816X_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_pci_816x_clkdm = {
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.name = "default_pci_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI816X_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain default_l3_slow_816x_clkdm = {
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.name = "default_l3_slow_clkdm",
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.pwrdm = { .name = "default_pwrdm" },
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.cm_inst = TI816X_CM_DEFAULT_MOD,
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.clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain *clockdomains_ti81xx[] __initdata = {
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&alwon_mpu_816x_clkdm,
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&alwon_l3_slow_81xx_clkdm,
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&alwon_l3_med_81xx_clkdm,
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&alwon_l3_fast_81xx_clkdm,
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&alwon_ethernet_81xx_clkdm,
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&mmu_81xx_clkdm,
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&mmu_cfg_81xx_clkdm,
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&active_gem_816x_clkdm,
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&ivahd0_816x_clkdm,
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&ivahd1_816x_clkdm,
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&ivahd2_816x_clkdm,
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&sgx_816x_clkdm,
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&default_l3_med_816x_clkdm,
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&default_ducati_816x_clkdm,
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&default_pci_816x_clkdm,
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&default_l3_slow_816x_clkdm,
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NULL,
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};
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void __init ti81xx_clockdomains_init(void)
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{
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clkdm_register_platform_funcs(&am33xx_clkdm_operations);
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clkdm_register_clkdms(clockdomains_ti81xx);
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clkdm_complete_init();
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}
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#endif
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61
arch/arm/mach-omap2/cm81xx.h
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61
arch/arm/mach-omap2/cm81xx.h
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@ -0,0 +1,61 @@
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/*
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* Clock domain register offsets for TI81XX.
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*
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* Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
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* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
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#define __ARCH_ARM_MACH_OMAP2_CM_TI81XX_H
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/* TI81XX common CM module offsets */
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#define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
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/* TI816X CM module offsets */
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#define TI816X_CM_ACTIVE_MOD 0x0400 /* 256B */
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#define TI816X_CM_DEFAULT_MOD 0x0500 /* 256B */
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#define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
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#define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
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#define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
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#define TI816X_CM_SGX_MOD 0x0900 /* 256B */
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/* ALWON */
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#define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
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#define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
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#define TI81XX_CM_ETHERNET_CLKDM 0x0004
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#define TI81XX_CM_MMU_CLKDM 0x000C
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#define TI81XX_CM_MMUCFG_CLKDM 0x0010
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#define TI81XX_CM_ALWON_MPU_CLKDM 0x001C
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#define TI81XX_CM_ALWON_L3_FAST_CLKDM 0x0030
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/* ACTIVE */
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#define TI816X_CM_ACTIVE_GEM_CLKDM 0x0000
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/* IVAHD0 */
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#define TI816X_CM_IVAHD0_CLKDM 0x0000
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/* IVAHD1 */
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#define TI816X_CM_IVAHD1_CLKDM 0x0000
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/* IVAHD2 */
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#define TI816X_CM_IVAHD2_CLKDM 0x0000
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/* SGX */
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#define TI816X_CM_SGX_CLKDM 0x0000
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/* DEFAULT */
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#define TI816X_CM_DEFAULT_L3_MED_CLKDM 0x0004
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#define TI816X_CM_DEFAULT_PCI_CLKDM 0x0010
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#define TI816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014
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#define TI816X_CM_DEFAULT_DUCATI_CLKDM 0x0018
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#endif
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@ -492,44 +492,6 @@ void __init am35xx_init_early(void)
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omap_clk_soc_init = am35xx_dt_clk_init;
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}
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void __init ti814x_init_early(void)
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{
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omap2_set_globals_tap(TI814X_CLASS,
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OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
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NULL);
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omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
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omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
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omap3xxx_check_revision();
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ti81xx_check_features();
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omap3xxx_voltagedomains_init();
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omap3xxx_powerdomains_init();
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omap3xxx_clockdomains_init();
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omap3xxx_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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}
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void __init ti816x_init_early(void)
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{
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omap2_set_globals_tap(TI816X_CLASS,
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OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
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NULL);
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omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
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omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
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omap3xxx_check_revision();
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ti81xx_check_features();
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omap3xxx_voltagedomains_init();
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omap3xxx_powerdomains_init();
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omap3xxx_clockdomains_init();
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omap3xxx_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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}
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void __init omap3_init_late(void)
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{
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omap_common_late_init();
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@ -572,6 +534,46 @@ void __init ti81xx_init_late(void)
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}
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#endif
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#ifdef CONFIG_SOC_TI81XX
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void __init ti814x_init_early(void)
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{
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omap2_set_globals_tap(TI814X_CLASS,
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OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
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NULL);
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omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
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omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
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omap3xxx_check_revision();
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ti81xx_check_features();
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omap3xxx_voltagedomains_init();
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omap3xxx_powerdomains_init();
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ti81xx_clockdomains_init();
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omap3xxx_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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}
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void __init ti816x_init_early(void)
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{
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omap2_set_globals_tap(TI816X_CLASS,
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OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
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omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
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NULL);
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omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
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omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
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omap3xxx_check_revision();
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ti81xx_check_features();
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omap3xxx_voltagedomains_init();
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omap3xxx_powerdomains_init();
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ti81xx_clockdomains_init();
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omap3xxx_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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}
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#endif
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#ifdef CONFIG_SOC_AM33XX
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void __init am33xx_init_early(void)
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{
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