Merge branch 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes: "adds support for the asynchronous DMA engines on r6xx-SI. These engines are used for ttm bo moves and VM page table updates currently. They could also be exposed via the CS ioctl for userspace use, but I haven't had a chance to add proper CS checker patches for them yet. These patches have been tested extensively internally for months, so they should be pretty solid." * 'drm-next-3.8' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: use DMA engine for VM page table updates on SI drm/radeon: add dma engine support for vm pt updates on si (v2) drm/radeon: use DMA engine for VM page table updates on cayman/TN drm/radeon: add dma engine support for vm pt updates on ni (v5) drm/radeon: use async dma for ttm buffer moves on 6xx-SI drm/radeon/kms: add support for dma rings to radeon_test_moves() drm/radeon/kms: Add initial support for async DMA on SI drm/radeon/kms: Add initial support for async DMA on cayman/TN drm/radeon/kms: Add initial support for async DMA on evergreen drm/radeon/kms: Add initial support for async DMA on r6xx/r7xx
This commit is contained in:
commit
a636a98291
14 changed files with 1739 additions and 98 deletions
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@ -2034,6 +2034,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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WREG32(GB_ADDR_CONFIG, gb_addr_config);
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WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
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WREG32(HDP_ADDR_CONFIG, gb_addr_config);
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WREG32(DMA_TILING_CONFIG, gb_addr_config);
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tmp = gb_addr_config & NUM_PIPES_MASK;
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tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
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@ -2403,8 +2404,12 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
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CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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cayman_cp_int_cntl_setup(rdev, 1, 0);
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cayman_cp_int_cntl_setup(rdev, 2, 0);
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tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
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WREG32(CAYMAN_DMA1_CNTL, tmp);
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} else
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WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
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WREG32(DMA_CNTL, tmp);
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WREG32(GRBM_INT_CNTL, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
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WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
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@ -2457,6 +2462,7 @@ int evergreen_irq_set(struct radeon_device *rdev)
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u32 grbm_int_cntl = 0;
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u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
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u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
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u32 dma_cntl, dma_cntl1 = 0;
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if (!rdev->irq.installed) {
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WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
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@ -2484,6 +2490,8 @@ int evergreen_irq_set(struct radeon_device *rdev)
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afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
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afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
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dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
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if (rdev->family >= CHIP_CAYMAN) {
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/* enable CP interrupts on all rings */
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if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
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@ -2506,6 +2514,19 @@ int evergreen_irq_set(struct radeon_device *rdev)
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}
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}
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if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
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DRM_DEBUG("r600_irq_set: sw int dma\n");
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dma_cntl |= TRAP_ENABLE;
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}
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if (rdev->family >= CHIP_CAYMAN) {
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dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
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if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
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DRM_DEBUG("r600_irq_set: sw int dma1\n");
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dma_cntl1 |= TRAP_ENABLE;
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}
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}
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if (rdev->irq.crtc_vblank_int[0] ||
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atomic_read(&rdev->irq.pflip[0])) {
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DRM_DEBUG("evergreen_irq_set: vblank 0\n");
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@ -2591,6 +2612,12 @@ int evergreen_irq_set(struct radeon_device *rdev)
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cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
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} else
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WREG32(CP_INT_CNTL, cp_int_cntl);
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WREG32(DMA_CNTL, dma_cntl);
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if (rdev->family >= CHIP_CAYMAN)
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WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
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WREG32(GRBM_INT_CNTL, grbm_int_cntl);
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WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
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@ -3126,9 +3153,19 @@ int evergreen_irq_process(struct radeon_device *rdev)
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} else
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radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
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break;
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case 224: /* DMA trap event */
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DRM_DEBUG("IH: DMA trap\n");
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radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
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break;
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case 233: /* GUI IDLE */
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DRM_DEBUG("IH: GUI idle\n");
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break;
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case 244: /* DMA trap event */
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if (rdev->family >= CHIP_CAYMAN) {
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DRM_DEBUG("IH: DMA1 trap\n");
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radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
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}
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break;
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default:
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DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
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break;
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@ -3154,6 +3191,143 @@ int evergreen_irq_process(struct radeon_device *rdev)
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return IRQ_HANDLED;
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}
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/**
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* evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
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*
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* @rdev: radeon_device pointer
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* @fence: radeon fence object
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*
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* Add a DMA fence packet to the ring to write
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* the fence seq number and DMA trap packet to generate
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* an interrupt if needed (evergreen-SI).
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*/
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void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
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/* write the fence */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
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radeon_ring_write(ring, addr & 0xfffffffc);
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
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radeon_ring_write(ring, fence->seq);
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/* generate an interrupt */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
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/* flush HDP */
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
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radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
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radeon_ring_write(ring, 1);
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}
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/**
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* evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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*
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* Schedule an IB in the DMA ring (evergreen).
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*/
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void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
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struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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if (rdev->wb.enabled) {
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u32 next_rptr = ring->wptr + 4;
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while ((next_rptr & 7) != 5)
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next_rptr++;
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next_rptr += 3;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
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radeon_ring_write(ring, next_rptr);
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}
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/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
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* Pad as necessary with NOPs.
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*/
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while ((ring->wptr & 7) != 5)
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
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radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
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radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
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}
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/**
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* evergreen_copy_dma - copy pages using the DMA engine
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*
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* @rdev: radeon_device pointer
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* @src_offset: src GPU address
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* @dst_offset: dst GPU address
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* @num_gpu_pages: number of GPU pages to xfer
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* @fence: radeon fence object
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*
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* Copy GPU paging using the DMA engine (evergreen-cayman).
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* Used by the radeon ttm implementation to move pages if
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* registered as the asic copy callback.
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*/
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int evergreen_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct radeon_fence **fence)
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{
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struct radeon_semaphore *sem = NULL;
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int ring_index = rdev->asic->copy.dma_ring_index;
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struct radeon_ring *ring = &rdev->ring[ring_index];
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u32 size_in_dw, cur_size_in_dw;
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int i, num_loops;
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int r = 0;
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r = radeon_semaphore_create(rdev, &sem);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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return r;
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}
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size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
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num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
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r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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radeon_semaphore_free(rdev, &sem, NULL);
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return r;
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}
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if (radeon_fence_need_sync(*fence, ring->idx)) {
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radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
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ring->idx);
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radeon_fence_note_sync(*fence, ring->idx);
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} else {
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radeon_semaphore_free(rdev, &sem, NULL);
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}
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for (i = 0; i < num_loops; i++) {
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cur_size_in_dw = size_in_dw;
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if (cur_size_in_dw > 0xFFFFF)
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cur_size_in_dw = 0xFFFFF;
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size_in_dw -= cur_size_in_dw;
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radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
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radeon_ring_write(ring, dst_offset & 0xfffffffc);
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radeon_ring_write(ring, src_offset & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
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radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
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src_offset += cur_size_in_dw * 4;
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dst_offset += cur_size_in_dw * 4;
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}
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r = radeon_fence_emit(rdev, fence, ring->idx);
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if (r) {
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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radeon_ring_unlock_commit(rdev, ring);
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radeon_semaphore_free(rdev, &sem, *fence);
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return r;
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}
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static int evergreen_startup(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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@ -3217,6 +3391,12 @@ static int evergreen_startup(struct radeon_device *rdev)
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return r;
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}
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r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
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return r;
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}
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/* Enable IRQ */
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r = r600_irq_init(rdev);
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if (r) {
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@ -3231,10 +3411,21 @@ static int evergreen_startup(struct radeon_device *rdev)
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0, 0xfffff, RADEON_CP_PACKET2);
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if (r)
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return r;
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ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
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DMA_RB_RPTR, DMA_RB_WPTR,
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2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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if (r)
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return r;
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r = evergreen_cp_load_microcode(rdev);
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if (r)
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return r;
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r = evergreen_cp_resume(rdev);
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if (r)
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return r;
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r = r600_dma_resume(rdev);
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if (r)
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return r;
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@ -3283,11 +3474,9 @@ int evergreen_resume(struct radeon_device *rdev)
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int evergreen_suspend(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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r600_audio_fini(rdev);
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r700_cp_stop(rdev);
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ring->ready = false;
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r600_dma_stop(rdev);
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evergreen_irq_suspend(rdev);
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radeon_wb_disable(rdev);
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evergreen_pcie_gart_disable(rdev);
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@ -3364,6 +3553,9 @@ int evergreen_init(struct radeon_device *rdev)
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
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r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
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rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
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r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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|
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|
@ -3376,6 +3568,7 @@ int evergreen_init(struct radeon_device *rdev)
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if (r) {
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dev_err(rdev->dev, "disabling GPU acceleration\n");
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r700_cp_fini(rdev);
|
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r600_dma_fini(rdev);
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r600_irq_fini(rdev);
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radeon_wb_fini(rdev);
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radeon_ib_pool_fini(rdev);
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@ -3403,6 +3596,7 @@ void evergreen_fini(struct radeon_device *rdev)
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r600_audio_fini(rdev);
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r600_blit_fini(rdev);
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r700_cp_fini(rdev);
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r600_dma_fini(rdev);
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r600_irq_fini(rdev);
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radeon_wb_fini(rdev);
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radeon_ib_pool_fini(rdev);
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|
|
|
@ -905,6 +905,37 @@
|
|||
# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
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||||
# define DC_HPDx_EN (1 << 28)
|
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|
||||
/* ASYNC DMA */
|
||||
#define DMA_RB_RPTR 0xd008
|
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#define DMA_RB_WPTR 0xd00c
|
||||
|
||||
#define DMA_CNTL 0xd02c
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# define TRAP_ENABLE (1 << 0)
|
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# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
|
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# define SEM_WAIT_INT_ENABLE (1 << 2)
|
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# define DATA_SWAP_ENABLE (1 << 3)
|
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# define FENCE_SWAP_ENABLE (1 << 4)
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# define CTXEMPTY_INT_ENABLE (1 << 28)
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#define DMA_TILING_CONFIG 0xD0B8
|
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|
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#define CAYMAN_DMA1_CNTL 0xd82c
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|
||||
/* async DMA packets */
|
||||
#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
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(((t) & 0x1) << 23) | \
|
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(((s) & 0x1) << 22) | \
|
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(((n) & 0xFFFFF) << 0))
|
||||
/* async DMA Packet types */
|
||||
#define DMA_PACKET_WRITE 0x2
|
||||
#define DMA_PACKET_COPY 0x3
|
||||
#define DMA_PACKET_INDIRECT_BUFFER 0x4
|
||||
#define DMA_PACKET_SEMAPHORE 0x5
|
||||
#define DMA_PACKET_FENCE 0x6
|
||||
#define DMA_PACKET_TRAP 0x7
|
||||
#define DMA_PACKET_SRBM_WRITE 0x9
|
||||
#define DMA_PACKET_CONSTANT_FILL 0xd
|
||||
#define DMA_PACKET_NOP 0xf
|
||||
|
||||
/* PCIE link stuff */
|
||||
#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
|
||||
#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
|
||||
|
|
|
@ -611,6 +611,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
|
|||
WREG32(GB_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
|
||||
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
|
||||
|
||||
tmp = gb_addr_config & NUM_PIPES_MASK;
|
||||
tmp = r6xx_remap_render_backend(rdev, tmp,
|
||||
|
@ -915,6 +917,7 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
|
|||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
|
||||
WREG32(SCRATCH_UMSK, 0);
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1128,6 +1131,181 @@ static int cayman_cp_resume(struct radeon_device *rdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* DMA
|
||||
* Starting with R600, the GPU has an asynchronous
|
||||
* DMA engine. The programming model is very similar
|
||||
* to the 3D engine (ring buffer, IBs, etc.), but the
|
||||
* DMA controller has it's own packet format that is
|
||||
* different form the PM4 format used by the 3D engine.
|
||||
* It supports copying data, writing embedded data,
|
||||
* solid fills, and a number of other things. It also
|
||||
* has support for tiling/detiling of buffers.
|
||||
* Cayman and newer support two asynchronous DMA engines.
|
||||
*/
|
||||
/**
|
||||
* cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ib: IB object to schedule
|
||||
*
|
||||
* Schedule an IB in the DMA ring (cayman-SI).
|
||||
*/
|
||||
void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
|
||||
struct radeon_ib *ib)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[ib->ring];
|
||||
|
||||
if (rdev->wb.enabled) {
|
||||
u32 next_rptr = ring->wptr + 4;
|
||||
while ((next_rptr & 7) != 5)
|
||||
next_rptr++;
|
||||
next_rptr += 3;
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
|
||||
radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
|
||||
radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
|
||||
radeon_ring_write(ring, next_rptr);
|
||||
}
|
||||
|
||||
/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
|
||||
* Pad as necessary with NOPs.
|
||||
*/
|
||||
while ((ring->wptr & 7) != 5)
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
|
||||
radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
|
||||
radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
|
||||
radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* cayman_dma_stop - stop the async dma engines
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Stop the async dma engines (cayman-SI).
|
||||
*/
|
||||
void cayman_dma_stop(struct radeon_device *rdev)
|
||||
{
|
||||
u32 rb_cntl;
|
||||
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
|
||||
/* dma0 */
|
||||
rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
|
||||
rb_cntl &= ~DMA_RB_ENABLE;
|
||||
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
|
||||
|
||||
/* dma1 */
|
||||
rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
|
||||
rb_cntl &= ~DMA_RB_ENABLE;
|
||||
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
|
||||
|
||||
rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
|
||||
rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
|
||||
}
|
||||
|
||||
/**
|
||||
* cayman_dma_resume - setup and start the async dma engines
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Set up the DMA ring buffers and enable them. (cayman-SI).
|
||||
* Returns 0 for success, error for failure.
|
||||
*/
|
||||
int cayman_dma_resume(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring;
|
||||
u32 rb_cntl, dma_cntl;
|
||||
u32 rb_bufsz;
|
||||
u32 reg_offset, wb_offset;
|
||||
int i, r;
|
||||
|
||||
/* Reset dma */
|
||||
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
|
||||
RREG32(SRBM_SOFT_RESET);
|
||||
udelay(50);
|
||||
WREG32(SRBM_SOFT_RESET, 0);
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
if (i == 0) {
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
reg_offset = DMA0_REGISTER_OFFSET;
|
||||
wb_offset = R600_WB_DMA_RPTR_OFFSET;
|
||||
} else {
|
||||
ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
|
||||
reg_offset = DMA1_REGISTER_OFFSET;
|
||||
wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
|
||||
}
|
||||
|
||||
WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
|
||||
WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
|
||||
|
||||
/* Set ring buffer size in dwords */
|
||||
rb_bufsz = drm_order(ring->ring_size / 4);
|
||||
rb_cntl = rb_bufsz << 1;
|
||||
#ifdef __BIG_ENDIAN
|
||||
rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
|
||||
#endif
|
||||
WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
|
||||
|
||||
/* Initialize the ring buffer's read and write pointers */
|
||||
WREG32(DMA_RB_RPTR + reg_offset, 0);
|
||||
WREG32(DMA_RB_WPTR + reg_offset, 0);
|
||||
|
||||
/* set the wb address whether it's enabled or not */
|
||||
WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
|
||||
upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
|
||||
WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
|
||||
((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
|
||||
|
||||
if (rdev->wb.enabled)
|
||||
rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
|
||||
|
||||
WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
|
||||
|
||||
/* enable DMA IBs */
|
||||
WREG32(DMA_IB_CNTL + reg_offset, DMA_IB_ENABLE | CMD_VMID_FORCE);
|
||||
|
||||
dma_cntl = RREG32(DMA_CNTL + reg_offset);
|
||||
dma_cntl &= ~CTXEMPTY_INT_ENABLE;
|
||||
WREG32(DMA_CNTL + reg_offset, dma_cntl);
|
||||
|
||||
ring->wptr = 0;
|
||||
WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
|
||||
|
||||
ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
|
||||
|
||||
WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
|
||||
|
||||
ring->ready = true;
|
||||
|
||||
r = radeon_ring_test(rdev, ring->idx, ring);
|
||||
if (r) {
|
||||
ring->ready = false;
|
||||
return r;
|
||||
}
|
||||
}
|
||||
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cayman_dma_fini - tear down the async dma engines
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Stop the async dma engines and free the rings (cayman-SI).
|
||||
*/
|
||||
void cayman_dma_fini(struct radeon_device *rdev)
|
||||
{
|
||||
cayman_dma_stop(rdev);
|
||||
radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
|
||||
radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
|
||||
}
|
||||
|
||||
static int cayman_gpu_soft_reset(struct radeon_device *rdev)
|
||||
{
|
||||
struct evergreen_mc_save save;
|
||||
|
@ -1218,6 +1396,32 @@ int cayman_asic_reset(struct radeon_device *rdev)
|
|||
return cayman_gpu_soft_reset(rdev);
|
||||
}
|
||||
|
||||
/**
|
||||
* cayman_dma_is_lockup - Check if the DMA engine is locked up
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon_ring structure holding ring information
|
||||
*
|
||||
* Check if the async DMA engine is locked up (cayman-SI).
|
||||
* Returns true if the engine appears to be locked up, false if not.
|
||||
*/
|
||||
bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
|
||||
{
|
||||
u32 dma_status_reg;
|
||||
|
||||
if (ring->idx == R600_RING_TYPE_DMA_INDEX)
|
||||
dma_status_reg = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
|
||||
else
|
||||
dma_status_reg = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
|
||||
if (dma_status_reg & DMA_IDLE) {
|
||||
radeon_ring_lockup_update(ring);
|
||||
return false;
|
||||
}
|
||||
/* force ring activities */
|
||||
radeon_ring_force_activity(rdev, ring);
|
||||
return radeon_ring_test_lockup(rdev, ring);
|
||||
}
|
||||
|
||||
static int cayman_startup(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
|
@ -1299,6 +1503,18 @@ static int cayman_startup(struct radeon_device *rdev)
|
|||
return r;
|
||||
}
|
||||
|
||||
r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
r = r600_irq_init(rdev);
|
||||
if (r) {
|
||||
|
@ -1313,6 +1529,23 @@ static int cayman_startup(struct radeon_device *rdev)
|
|||
0, 0xfffff, RADEON_CP_PACKET2);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
|
||||
DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
|
||||
DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
|
||||
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
|
||||
DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
|
||||
DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
|
||||
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = cayman_cp_load_microcode(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
@ -1320,6 +1553,10 @@ static int cayman_startup(struct radeon_device *rdev)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
r = cayman_dma_resume(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_ib_pool_init(rdev);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
||||
|
@ -1364,7 +1601,7 @@ int cayman_suspend(struct radeon_device *rdev)
|
|||
{
|
||||
r600_audio_fini(rdev);
|
||||
cayman_cp_enable(rdev, false);
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
||||
cayman_dma_stop(rdev);
|
||||
evergreen_irq_suspend(rdev);
|
||||
radeon_wb_disable(rdev);
|
||||
cayman_pcie_gart_disable(rdev);
|
||||
|
@ -1431,6 +1668,14 @@ int cayman_init(struct radeon_device *rdev)
|
|||
ring->ring_obj = NULL;
|
||||
r600_ring_init(rdev, ring, 1024 * 1024);
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
ring->ring_obj = NULL;
|
||||
r600_ring_init(rdev, ring, 64 * 1024);
|
||||
|
||||
ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
|
||||
ring->ring_obj = NULL;
|
||||
r600_ring_init(rdev, ring, 64 * 1024);
|
||||
|
||||
rdev->ih.ring_obj = NULL;
|
||||
r600_ih_ring_init(rdev, 64 * 1024);
|
||||
|
||||
|
@ -1443,6 +1688,7 @@ int cayman_init(struct radeon_device *rdev)
|
|||
if (r) {
|
||||
dev_err(rdev->dev, "disabling GPU acceleration\n");
|
||||
cayman_cp_fini(rdev);
|
||||
cayman_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
if (rdev->flags & RADEON_IS_IGP)
|
||||
si_rlc_fini(rdev);
|
||||
|
@ -1473,6 +1719,7 @@ void cayman_fini(struct radeon_device *rdev)
|
|||
{
|
||||
r600_blit_fini(rdev);
|
||||
cayman_cp_fini(rdev);
|
||||
cayman_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
if (rdev->flags & RADEON_IS_IGP)
|
||||
si_rlc_fini(rdev);
|
||||
|
@ -1548,30 +1795,57 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
|
|||
{
|
||||
struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
|
||||
uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
|
||||
uint64_t value;
|
||||
unsigned ndw;
|
||||
|
||||
while (count) {
|
||||
unsigned ndw = 1 + count * 2;
|
||||
if (ndw > 0x3FFF)
|
||||
ndw = 0x3FFF;
|
||||
if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
|
||||
while (count) {
|
||||
ndw = 1 + count * 2;
|
||||
if (ndw > 0x3FFF)
|
||||
ndw = 0x3FFF;
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
|
||||
radeon_ring_write(ring, pe);
|
||||
radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
|
||||
for (; ndw > 1; ndw -= 2, --count, pe += 8) {
|
||||
uint64_t value = 0;
|
||||
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
||||
value = radeon_vm_map_gart(rdev, addr);
|
||||
value &= 0xFFFFFFFFFFFFF000ULL;
|
||||
addr += incr;
|
||||
|
||||
} else if (flags & RADEON_VM_PAGE_VALID) {
|
||||
value = addr;
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
|
||||
radeon_ring_write(ring, pe);
|
||||
radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
|
||||
for (; ndw > 1; ndw -= 2, --count, pe += 8) {
|
||||
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
||||
value = radeon_vm_map_gart(rdev, addr);
|
||||
value &= 0xFFFFFFFFFFFFF000ULL;
|
||||
} else if (flags & RADEON_VM_PAGE_VALID) {
|
||||
value = addr;
|
||||
} else {
|
||||
value = 0;
|
||||
}
|
||||
addr += incr;
|
||||
value |= r600_flags;
|
||||
radeon_ring_write(ring, value);
|
||||
radeon_ring_write(ring, upper_32_bits(value));
|
||||
}
|
||||
}
|
||||
} else {
|
||||
while (count) {
|
||||
ndw = count * 2;
|
||||
if (ndw > 0xFFFFE)
|
||||
ndw = 0xFFFFE;
|
||||
|
||||
value |= r600_flags;
|
||||
radeon_ring_write(ring, value);
|
||||
radeon_ring_write(ring, upper_32_bits(value));
|
||||
/* for non-physically contiguous pages (system) */
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw));
|
||||
radeon_ring_write(ring, pe);
|
||||
radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
|
||||
for (; ndw > 0; ndw -= 2, --count, pe += 8) {
|
||||
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
||||
value = radeon_vm_map_gart(rdev, addr);
|
||||
value &= 0xFFFFFFFFFFFFF000ULL;
|
||||
} else if (flags & RADEON_VM_PAGE_VALID) {
|
||||
value = addr;
|
||||
} else {
|
||||
value = 0;
|
||||
}
|
||||
addr += incr;
|
||||
value |= r600_flags;
|
||||
radeon_ring_write(ring, value);
|
||||
radeon_ring_write(ring, upper_32_bits(value));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -1606,3 +1880,26 @@ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
|||
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
|
||||
radeon_ring_write(ring, 0x0);
|
||||
}
|
||||
|
||||
void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[ridx];
|
||||
|
||||
if (vm == NULL)
|
||||
return;
|
||||
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
|
||||
radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
|
||||
radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
|
||||
|
||||
/* flush hdp cache */
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
|
||||
radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
|
||||
radeon_ring_write(ring, 1);
|
||||
|
||||
/* bits 0-7 are the VM contexts0-7 */
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
|
||||
radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
|
||||
radeon_ring_write(ring, 1 << vm->id);
|
||||
}
|
||||
|
||||
|
|
|
@ -50,6 +50,24 @@
|
|||
#define VMID(x) (((x) & 0x7) << 0)
|
||||
#define SRBM_STATUS 0x0E50
|
||||
|
||||
#define SRBM_SOFT_RESET 0x0E60
|
||||
#define SOFT_RESET_BIF (1 << 1)
|
||||
#define SOFT_RESET_CG (1 << 2)
|
||||
#define SOFT_RESET_DC (1 << 5)
|
||||
#define SOFT_RESET_DMA1 (1 << 6)
|
||||
#define SOFT_RESET_GRBM (1 << 8)
|
||||
#define SOFT_RESET_HDP (1 << 9)
|
||||
#define SOFT_RESET_IH (1 << 10)
|
||||
#define SOFT_RESET_MC (1 << 11)
|
||||
#define SOFT_RESET_RLC (1 << 13)
|
||||
#define SOFT_RESET_ROM (1 << 14)
|
||||
#define SOFT_RESET_SEM (1 << 15)
|
||||
#define SOFT_RESET_VMC (1 << 17)
|
||||
#define SOFT_RESET_DMA (1 << 20)
|
||||
#define SOFT_RESET_TST (1 << 21)
|
||||
#define SOFT_RESET_REGBB (1 << 22)
|
||||
#define SOFT_RESET_ORB (1 << 23)
|
||||
|
||||
#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
|
||||
#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
|
||||
#define RESPONSE_TYPE_MASK 0x000000F0
|
||||
|
@ -599,5 +617,62 @@
|
|||
#define PACKET3_SET_APPEND_CNT 0x75
|
||||
#define PACKET3_ME_WRITE 0x7A
|
||||
|
||||
/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
|
||||
#define DMA0_REGISTER_OFFSET 0x0 /* not a register */
|
||||
#define DMA1_REGISTER_OFFSET 0x800 /* not a register */
|
||||
|
||||
#define DMA_RB_CNTL 0xd000
|
||||
# define DMA_RB_ENABLE (1 << 0)
|
||||
# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
|
||||
# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
|
||||
# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
|
||||
# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
|
||||
# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
|
||||
#define DMA_RB_BASE 0xd004
|
||||
#define DMA_RB_RPTR 0xd008
|
||||
#define DMA_RB_WPTR 0xd00c
|
||||
|
||||
#define DMA_RB_RPTR_ADDR_HI 0xd01c
|
||||
#define DMA_RB_RPTR_ADDR_LO 0xd020
|
||||
|
||||
#define DMA_IB_CNTL 0xd024
|
||||
# define DMA_IB_ENABLE (1 << 0)
|
||||
# define DMA_IB_SWAP_ENABLE (1 << 4)
|
||||
# define CMD_VMID_FORCE (1 << 31)
|
||||
#define DMA_IB_RPTR 0xd028
|
||||
#define DMA_CNTL 0xd02c
|
||||
# define TRAP_ENABLE (1 << 0)
|
||||
# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
|
||||
# define SEM_WAIT_INT_ENABLE (1 << 2)
|
||||
# define DATA_SWAP_ENABLE (1 << 3)
|
||||
# define FENCE_SWAP_ENABLE (1 << 4)
|
||||
# define CTXEMPTY_INT_ENABLE (1 << 28)
|
||||
#define DMA_STATUS_REG 0xd034
|
||||
# define DMA_IDLE (1 << 0)
|
||||
#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
|
||||
#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
|
||||
#define DMA_TILING_CONFIG 0xd0b8
|
||||
#define DMA_MODE 0xd0bc
|
||||
|
||||
#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
|
||||
(((t) & 0x1) << 23) | \
|
||||
(((s) & 0x1) << 22) | \
|
||||
(((n) & 0xFFFFF) << 0))
|
||||
|
||||
#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
|
||||
(((vmid) & 0xF) << 20) | \
|
||||
(((n) & 0xFFFFF) << 0))
|
||||
|
||||
/* async DMA Packet types */
|
||||
#define DMA_PACKET_WRITE 0x2
|
||||
#define DMA_PACKET_COPY 0x3
|
||||
#define DMA_PACKET_INDIRECT_BUFFER 0x4
|
||||
#define DMA_PACKET_SEMAPHORE 0x5
|
||||
#define DMA_PACKET_FENCE 0x6
|
||||
#define DMA_PACKET_TRAP 0x7
|
||||
#define DMA_PACKET_SRBM_WRITE 0x9
|
||||
#define DMA_PACKET_CONSTANT_FILL 0xd
|
||||
#define DMA_PACKET_NOP 0xf
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
@ -1370,6 +1370,29 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
return radeon_ring_test_lockup(rdev, ring);
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_dma_is_lockup - Check if the DMA engine is locked up
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon_ring structure holding ring information
|
||||
*
|
||||
* Check if the async DMA engine is locked up (r6xx-evergreen).
|
||||
* Returns true if the engine appears to be locked up, false if not.
|
||||
*/
|
||||
bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
|
||||
{
|
||||
u32 dma_status_reg;
|
||||
|
||||
dma_status_reg = RREG32(DMA_STATUS_REG);
|
||||
if (dma_status_reg & DMA_IDLE) {
|
||||
radeon_ring_lockup_update(ring);
|
||||
return false;
|
||||
}
|
||||
/* force ring activities */
|
||||
radeon_ring_force_activity(rdev, ring);
|
||||
return radeon_ring_test_lockup(rdev, ring);
|
||||
}
|
||||
|
||||
int r600_asic_reset(struct radeon_device *rdev)
|
||||
{
|
||||
return r600_gpu_soft_reset(rdev);
|
||||
|
@ -1588,6 +1611,7 @@ static void r600_gpu_init(struct radeon_device *rdev)
|
|||
WREG32(GB_TILING_CONFIG, tiling_config);
|
||||
WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
|
||||
WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
|
||||
WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
|
||||
|
||||
tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
|
||||
WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
|
||||
|
@ -1865,6 +1889,7 @@ void r600_cp_stop(struct radeon_device *rdev)
|
|||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
|
||||
WREG32(SCRATCH_UMSK, 0);
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
||||
}
|
||||
|
||||
int r600_init_microcode(struct radeon_device *rdev)
|
||||
|
@ -2190,6 +2215,128 @@ void r600_cp_fini(struct radeon_device *rdev)
|
|||
radeon_scratch_free(rdev, ring->rptr_save_reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* DMA
|
||||
* Starting with R600, the GPU has an asynchronous
|
||||
* DMA engine. The programming model is very similar
|
||||
* to the 3D engine (ring buffer, IBs, etc.), but the
|
||||
* DMA controller has it's own packet format that is
|
||||
* different form the PM4 format used by the 3D engine.
|
||||
* It supports copying data, writing embedded data,
|
||||
* solid fills, and a number of other things. It also
|
||||
* has support for tiling/detiling of buffers.
|
||||
*/
|
||||
/**
|
||||
* r600_dma_stop - stop the async dma engine
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Stop the async dma engine (r6xx-evergreen).
|
||||
*/
|
||||
void r600_dma_stop(struct radeon_device *rdev)
|
||||
{
|
||||
u32 rb_cntl = RREG32(DMA_RB_CNTL);
|
||||
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
|
||||
rb_cntl &= ~DMA_RB_ENABLE;
|
||||
WREG32(DMA_RB_CNTL, rb_cntl);
|
||||
|
||||
rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_dma_resume - setup and start the async dma engine
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Set up the DMA ring buffer and enable it. (r6xx-evergreen).
|
||||
* Returns 0 for success, error for failure.
|
||||
*/
|
||||
int r600_dma_resume(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
u32 rb_cntl, dma_cntl;
|
||||
u32 rb_bufsz;
|
||||
int r;
|
||||
|
||||
/* Reset dma */
|
||||
if (rdev->family >= CHIP_RV770)
|
||||
WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
|
||||
else
|
||||
WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
|
||||
RREG32(SRBM_SOFT_RESET);
|
||||
udelay(50);
|
||||
WREG32(SRBM_SOFT_RESET, 0);
|
||||
|
||||
WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
|
||||
WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
|
||||
|
||||
/* Set ring buffer size in dwords */
|
||||
rb_bufsz = drm_order(ring->ring_size / 4);
|
||||
rb_cntl = rb_bufsz << 1;
|
||||
#ifdef __BIG_ENDIAN
|
||||
rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
|
||||
#endif
|
||||
WREG32(DMA_RB_CNTL, rb_cntl);
|
||||
|
||||
/* Initialize the ring buffer's read and write pointers */
|
||||
WREG32(DMA_RB_RPTR, 0);
|
||||
WREG32(DMA_RB_WPTR, 0);
|
||||
|
||||
/* set the wb address whether it's enabled or not */
|
||||
WREG32(DMA_RB_RPTR_ADDR_HI,
|
||||
upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
|
||||
WREG32(DMA_RB_RPTR_ADDR_LO,
|
||||
((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
|
||||
|
||||
if (rdev->wb.enabled)
|
||||
rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
|
||||
|
||||
WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
|
||||
|
||||
/* enable DMA IBs */
|
||||
WREG32(DMA_IB_CNTL, DMA_IB_ENABLE);
|
||||
|
||||
dma_cntl = RREG32(DMA_CNTL);
|
||||
dma_cntl &= ~CTXEMPTY_INT_ENABLE;
|
||||
WREG32(DMA_CNTL, dma_cntl);
|
||||
|
||||
if (rdev->family >= CHIP_RV770)
|
||||
WREG32(DMA_MODE, 1);
|
||||
|
||||
ring->wptr = 0;
|
||||
WREG32(DMA_RB_WPTR, ring->wptr << 2);
|
||||
|
||||
ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
|
||||
|
||||
WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
|
||||
|
||||
ring->ready = true;
|
||||
|
||||
r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
|
||||
if (r) {
|
||||
ring->ready = false;
|
||||
return r;
|
||||
}
|
||||
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_dma_fini - tear down the async dma engine
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Stop the async dma engine and free the ring (r6xx-evergreen).
|
||||
*/
|
||||
void r600_dma_fini(struct radeon_device *rdev)
|
||||
{
|
||||
r600_dma_stop(rdev);
|
||||
radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
|
||||
}
|
||||
|
||||
/*
|
||||
* GPU scratch registers helpers function.
|
||||
|
@ -2246,6 +2393,64 @@ int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_dma_ring_test - simple async dma engine test
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon_ring structure holding ring information
|
||||
*
|
||||
* Test the DMA engine by writing using it to write an
|
||||
* value to memory. (r6xx-SI).
|
||||
* Returns 0 for success, error for failure.
|
||||
*/
|
||||
int r600_dma_ring_test(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
unsigned i;
|
||||
int r;
|
||||
void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
|
||||
u32 tmp;
|
||||
|
||||
if (!ptr) {
|
||||
DRM_ERROR("invalid vram scratch pointer\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
tmp = 0xCAFEDEAD;
|
||||
writel(tmp, ptr);
|
||||
|
||||
r = radeon_ring_lock(rdev, ring, 4);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
|
||||
return r;
|
||||
}
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
|
||||
radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
|
||||
radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
|
||||
radeon_ring_write(ring, 0xDEADBEEF);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
tmp = readl(ptr);
|
||||
if (tmp == 0xDEADBEEF)
|
||||
break;
|
||||
DRM_UDELAY(1);
|
||||
}
|
||||
|
||||
if (i < rdev->usec_timeout) {
|
||||
DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
|
||||
} else {
|
||||
DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
|
||||
ring->idx, tmp);
|
||||
r = -EINVAL;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* CP fences/semaphores
|
||||
*/
|
||||
|
||||
void r600_fence_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_fence *fence)
|
||||
{
|
||||
|
@ -2309,6 +2514,58 @@ void r600_semaphore_ring_emit(struct radeon_device *rdev,
|
|||
radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
|
||||
}
|
||||
|
||||
/*
|
||||
* DMA fences/semaphores
|
||||
*/
|
||||
|
||||
/**
|
||||
* r600_dma_fence_ring_emit - emit a fence on the DMA ring
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @fence: radeon fence object
|
||||
*
|
||||
* Add a DMA fence packet to the ring to write
|
||||
* the fence seq number and DMA trap packet to generate
|
||||
* an interrupt if needed (r6xx-r7xx).
|
||||
*/
|
||||
void r600_dma_fence_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_fence *fence)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[fence->ring];
|
||||
u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
|
||||
/* write the fence */
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
|
||||
radeon_ring_write(ring, addr & 0xfffffffc);
|
||||
radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
|
||||
radeon_ring_write(ring, fence->seq);
|
||||
/* generate an interrupt */
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon_ring structure holding ring information
|
||||
* @semaphore: radeon semaphore object
|
||||
* @emit_wait: wait or signal semaphore
|
||||
*
|
||||
* Add a DMA semaphore packet to the ring wait on or signal
|
||||
* other rings (r6xx-SI).
|
||||
*/
|
||||
void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring,
|
||||
struct radeon_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
u64 addr = semaphore->gpu_addr;
|
||||
u32 s = emit_wait ? 0 : 1;
|
||||
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
|
||||
radeon_ring_write(ring, addr & 0xfffffffc);
|
||||
radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
|
||||
}
|
||||
|
||||
int r600_copy_blit(struct radeon_device *rdev,
|
||||
uint64_t src_offset,
|
||||
uint64_t dst_offset,
|
||||
|
@ -2328,6 +2585,80 @@ int r600_copy_blit(struct radeon_device *rdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_copy_dma - copy pages using the DMA engine
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @src_offset: src GPU address
|
||||
* @dst_offset: dst GPU address
|
||||
* @num_gpu_pages: number of GPU pages to xfer
|
||||
* @fence: radeon fence object
|
||||
*
|
||||
* Copy GPU paging using the DMA engine (r6xx-r7xx).
|
||||
* Used by the radeon ttm implementation to move pages if
|
||||
* registered as the asic copy callback.
|
||||
*/
|
||||
int r600_copy_dma(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_gpu_pages,
|
||||
struct radeon_fence **fence)
|
||||
{
|
||||
struct radeon_semaphore *sem = NULL;
|
||||
int ring_index = rdev->asic->copy.dma_ring_index;
|
||||
struct radeon_ring *ring = &rdev->ring[ring_index];
|
||||
u32 size_in_dw, cur_size_in_dw;
|
||||
int i, num_loops;
|
||||
int r = 0;
|
||||
|
||||
r = radeon_semaphore_create(rdev, &sem);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: moving bo (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
|
||||
num_loops = DIV_ROUND_UP(size_in_dw, 0xffff);
|
||||
r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: moving bo (%d).\n", r);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
if (radeon_fence_need_sync(*fence, ring->idx)) {
|
||||
radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
|
||||
ring->idx);
|
||||
radeon_fence_note_sync(*fence, ring->idx);
|
||||
} else {
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
}
|
||||
|
||||
for (i = 0; i < num_loops; i++) {
|
||||
cur_size_in_dw = size_in_dw;
|
||||
if (cur_size_in_dw > 0xFFFF)
|
||||
cur_size_in_dw = 0xFFFF;
|
||||
size_in_dw -= cur_size_in_dw;
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
|
||||
radeon_ring_write(ring, dst_offset & 0xfffffffc);
|
||||
radeon_ring_write(ring, src_offset & 0xfffffffc);
|
||||
radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
|
||||
radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
|
||||
src_offset += cur_size_in_dw * 4;
|
||||
dst_offset += cur_size_in_dw * 4;
|
||||
}
|
||||
|
||||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
return r;
|
||||
}
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, *fence);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
|
||||
uint32_t tiling_flags, uint32_t pitch,
|
||||
uint32_t offset, uint32_t obj_size)
|
||||
|
@ -2343,7 +2674,7 @@ void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
|
|||
|
||||
static int r600_startup(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
struct radeon_ring *ring;
|
||||
int r;
|
||||
|
||||
/* enable pcie gen2 link */
|
||||
|
@ -2388,6 +2719,12 @@ static int r600_startup(struct radeon_device *rdev)
|
|||
return r;
|
||||
}
|
||||
|
||||
r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
r = r600_irq_init(rdev);
|
||||
if (r) {
|
||||
|
@ -2397,12 +2734,20 @@ static int r600_startup(struct radeon_device *rdev)
|
|||
}
|
||||
r600_irq_set(rdev);
|
||||
|
||||
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
|
||||
R600_CP_RB_RPTR, R600_CP_RB_WPTR,
|
||||
0, 0xfffff, RADEON_CP_PACKET2);
|
||||
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
|
||||
DMA_RB_RPTR, DMA_RB_WPTR,
|
||||
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = r600_cp_load_microcode(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
@ -2410,6 +2755,10 @@ static int r600_startup(struct radeon_device *rdev)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
r = r600_dma_resume(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_ib_pool_init(rdev);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
||||
|
@ -2465,7 +2814,7 @@ int r600_suspend(struct radeon_device *rdev)
|
|||
{
|
||||
r600_audio_fini(rdev);
|
||||
r600_cp_stop(rdev);
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
||||
r600_dma_stop(rdev);
|
||||
r600_irq_suspend(rdev);
|
||||
radeon_wb_disable(rdev);
|
||||
r600_pcie_gart_disable(rdev);
|
||||
|
@ -2538,6 +2887,9 @@ int r600_init(struct radeon_device *rdev)
|
|||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
|
||||
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
|
||||
|
||||
rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
|
||||
r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
|
||||
|
||||
rdev->ih.ring_obj = NULL;
|
||||
r600_ih_ring_init(rdev, 64 * 1024);
|
||||
|
||||
|
@ -2550,6 +2902,7 @@ int r600_init(struct radeon_device *rdev)
|
|||
if (r) {
|
||||
dev_err(rdev->dev, "disabling GPU acceleration\n");
|
||||
r600_cp_fini(rdev);
|
||||
r600_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
radeon_wb_fini(rdev);
|
||||
radeon_ib_pool_fini(rdev);
|
||||
|
@ -2566,6 +2919,7 @@ void r600_fini(struct radeon_device *rdev)
|
|||
r600_audio_fini(rdev);
|
||||
r600_blit_fini(rdev);
|
||||
r600_cp_fini(rdev);
|
||||
r600_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
radeon_wb_fini(rdev);
|
||||
radeon_ib_pool_fini(rdev);
|
||||
|
@ -2668,6 +3022,104 @@ int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_dma_ib_test - test an IB on the DMA engine
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon_ring structure holding ring information
|
||||
*
|
||||
* Test a simple IB in the DMA ring (r6xx-SI).
|
||||
* Returns 0 on success, error on failure.
|
||||
*/
|
||||
int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
||||
{
|
||||
struct radeon_ib ib;
|
||||
unsigned i;
|
||||
int r;
|
||||
void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
|
||||
u32 tmp = 0;
|
||||
|
||||
if (!ptr) {
|
||||
DRM_ERROR("invalid vram scratch pointer\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
tmp = 0xCAFEDEAD;
|
||||
writel(tmp, ptr);
|
||||
|
||||
r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to get ib (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
|
||||
ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
|
||||
ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
|
||||
ib.ptr[3] = 0xDEADBEEF;
|
||||
ib.length_dw = 4;
|
||||
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL);
|
||||
if (r) {
|
||||
radeon_ib_free(rdev, &ib);
|
||||
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
r = radeon_fence_wait(ib.fence, false);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: fence wait failed (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
tmp = readl(ptr);
|
||||
if (tmp == 0xDEADBEEF)
|
||||
break;
|
||||
DRM_UDELAY(1);
|
||||
}
|
||||
if (i < rdev->usec_timeout) {
|
||||
DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
|
||||
} else {
|
||||
DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
|
||||
r = -EINVAL;
|
||||
}
|
||||
radeon_ib_free(rdev, &ib);
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ib: IB object to schedule
|
||||
*
|
||||
* Schedule an IB in the DMA ring (r6xx-r7xx).
|
||||
*/
|
||||
void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[ib->ring];
|
||||
|
||||
if (rdev->wb.enabled) {
|
||||
u32 next_rptr = ring->wptr + 4;
|
||||
while ((next_rptr & 7) != 5)
|
||||
next_rptr++;
|
||||
next_rptr += 3;
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
|
||||
radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
|
||||
radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
|
||||
radeon_ring_write(ring, next_rptr);
|
||||
}
|
||||
|
||||
/* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
|
||||
* Pad as necessary with NOPs.
|
||||
*/
|
||||
while ((ring->wptr & 7) != 5)
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
|
||||
radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
|
||||
radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupts
|
||||
*
|
||||
|
@ -2859,6 +3311,8 @@ static void r600_disable_interrupt_state(struct radeon_device *rdev)
|
|||
u32 tmp;
|
||||
|
||||
WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
|
||||
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
|
||||
WREG32(DMA_CNTL, tmp);
|
||||
WREG32(GRBM_INT_CNTL, 0);
|
||||
WREG32(DxMODE_INT_MASK, 0);
|
||||
WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
|
||||
|
@ -3000,6 +3454,7 @@ int r600_irq_set(struct radeon_device *rdev)
|
|||
u32 grbm_int_cntl = 0;
|
||||
u32 hdmi0, hdmi1;
|
||||
u32 d1grph = 0, d2grph = 0;
|
||||
u32 dma_cntl;
|
||||
|
||||
if (!rdev->irq.installed) {
|
||||
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
|
||||
|
@ -3034,12 +3489,19 @@ int r600_irq_set(struct radeon_device *rdev)
|
|||
hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
|
||||
hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
|
||||
}
|
||||
dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
|
||||
|
||||
if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
|
||||
DRM_DEBUG("r600_irq_set: sw int\n");
|
||||
cp_int_cntl |= RB_INT_ENABLE;
|
||||
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
|
||||
}
|
||||
|
||||
if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
|
||||
DRM_DEBUG("r600_irq_set: sw int dma\n");
|
||||
dma_cntl |= TRAP_ENABLE;
|
||||
}
|
||||
|
||||
if (rdev->irq.crtc_vblank_int[0] ||
|
||||
atomic_read(&rdev->irq.pflip[0])) {
|
||||
DRM_DEBUG("r600_irq_set: vblank 0\n");
|
||||
|
@ -3084,6 +3546,7 @@ int r600_irq_set(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
WREG32(CP_INT_CNTL, cp_int_cntl);
|
||||
WREG32(DMA_CNTL, dma_cntl);
|
||||
WREG32(DxMODE_INT_MASK, mode_int);
|
||||
WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
|
||||
WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
|
||||
|
@ -3463,6 +3926,10 @@ int r600_irq_process(struct radeon_device *rdev)
|
|||
DRM_DEBUG("IH: CP EOP\n");
|
||||
radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
|
||||
break;
|
||||
case 224: /* DMA trap event */
|
||||
DRM_DEBUG("IH: DMA trap\n");
|
||||
radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
|
||||
break;
|
||||
case 233: /* GUI IDLE */
|
||||
DRM_DEBUG("IH: GUI idle\n");
|
||||
break;
|
||||
|
|
|
@ -590,9 +590,59 @@
|
|||
#define WAIT_2D_IDLECLEAN_bit (1 << 16)
|
||||
#define WAIT_3D_IDLECLEAN_bit (1 << 17)
|
||||
|
||||
/* async DMA */
|
||||
#define DMA_TILING_CONFIG 0x3ec4
|
||||
#define DMA_CONFIG 0x3e4c
|
||||
|
||||
#define DMA_RB_CNTL 0xd000
|
||||
# define DMA_RB_ENABLE (1 << 0)
|
||||
# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
|
||||
# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
|
||||
# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
|
||||
# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
|
||||
# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
|
||||
#define DMA_RB_BASE 0xd004
|
||||
#define DMA_RB_RPTR 0xd008
|
||||
#define DMA_RB_WPTR 0xd00c
|
||||
|
||||
#define DMA_RB_RPTR_ADDR_HI 0xd01c
|
||||
#define DMA_RB_RPTR_ADDR_LO 0xd020
|
||||
|
||||
#define DMA_IB_CNTL 0xd024
|
||||
# define DMA_IB_ENABLE (1 << 0)
|
||||
# define DMA_IB_SWAP_ENABLE (1 << 4)
|
||||
#define DMA_IB_RPTR 0xd028
|
||||
#define DMA_CNTL 0xd02c
|
||||
# define TRAP_ENABLE (1 << 0)
|
||||
# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
|
||||
# define SEM_WAIT_INT_ENABLE (1 << 2)
|
||||
# define DATA_SWAP_ENABLE (1 << 3)
|
||||
# define FENCE_SWAP_ENABLE (1 << 4)
|
||||
# define CTXEMPTY_INT_ENABLE (1 << 28)
|
||||
#define DMA_STATUS_REG 0xd034
|
||||
# define DMA_IDLE (1 << 0)
|
||||
#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044
|
||||
#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048
|
||||
#define DMA_MODE 0xd0bc
|
||||
|
||||
/* async DMA packets */
|
||||
#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
|
||||
(((t) & 0x1) << 23) | \
|
||||
(((s) & 0x1) << 22) | \
|
||||
(((n) & 0xFFFF) << 0))
|
||||
/* async DMA Packet types */
|
||||
#define DMA_PACKET_WRITE 0x2
|
||||
#define DMA_PACKET_COPY 0x3
|
||||
#define DMA_PACKET_INDIRECT_BUFFER 0x4
|
||||
#define DMA_PACKET_SEMAPHORE 0x5
|
||||
#define DMA_PACKET_FENCE 0x6
|
||||
#define DMA_PACKET_TRAP 0x7
|
||||
#define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */
|
||||
#define DMA_PACKET_NOP 0xf
|
||||
|
||||
#define IH_RB_CNTL 0x3e00
|
||||
# define IH_RB_ENABLE (1 << 0)
|
||||
# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
|
||||
# define IH_RB_SIZE(x) ((x) << 1) /* log2 */
|
||||
# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
|
||||
# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
|
||||
# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
|
||||
|
@ -637,7 +687,9 @@
|
|||
#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
|
||||
|
||||
#define SRBM_SOFT_RESET 0xe60
|
||||
# define SOFT_RESET_DMA (1 << 12)
|
||||
# define SOFT_RESET_RLC (1 << 13)
|
||||
# define RV770_SOFT_RESET_DMA (1 << 20)
|
||||
|
||||
#define CP_INT_CNTL 0xc124
|
||||
# define CNTX_BUSY_INT_ENABLE (1 << 19)
|
||||
|
|
|
@ -109,7 +109,7 @@ extern int radeon_lockup_timeout;
|
|||
#define RADEON_BIOS_NUM_SCRATCH 8
|
||||
|
||||
/* max number of rings */
|
||||
#define RADEON_NUM_RINGS 3
|
||||
#define RADEON_NUM_RINGS 5
|
||||
|
||||
/* fence seq are set to this number when signaled */
|
||||
#define RADEON_FENCE_SIGNALED_SEQ 0LL
|
||||
|
@ -122,6 +122,11 @@ extern int radeon_lockup_timeout;
|
|||
#define CAYMAN_RING_TYPE_CP1_INDEX 1
|
||||
#define CAYMAN_RING_TYPE_CP2_INDEX 2
|
||||
|
||||
/* R600+ has an async dma ring */
|
||||
#define R600_RING_TYPE_DMA_INDEX 3
|
||||
/* cayman add a second async dma ring */
|
||||
#define CAYMAN_RING_TYPE_DMA1_INDEX 4
|
||||
|
||||
/* hardcode those limit for now */
|
||||
#define RADEON_VA_IB_OFFSET (1 << 20)
|
||||
#define RADEON_VA_RESERVED_SIZE (8 << 20)
|
||||
|
@ -787,6 +792,15 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigne
|
|||
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
|
||||
|
||||
/* r600 async dma */
|
||||
void r600_dma_stop(struct radeon_device *rdev);
|
||||
int r600_dma_resume(struct radeon_device *rdev);
|
||||
void r600_dma_fini(struct radeon_device *rdev);
|
||||
|
||||
void cayman_dma_stop(struct radeon_device *rdev);
|
||||
int cayman_dma_resume(struct radeon_device *rdev);
|
||||
void cayman_dma_fini(struct radeon_device *rdev);
|
||||
|
||||
/*
|
||||
* CS.
|
||||
*/
|
||||
|
@ -883,7 +897,9 @@ struct radeon_wb {
|
|||
#define RADEON_WB_CP_RPTR_OFFSET 1024
|
||||
#define RADEON_WB_CP1_RPTR_OFFSET 1280
|
||||
#define RADEON_WB_CP2_RPTR_OFFSET 1536
|
||||
#define R600_WB_DMA_RPTR_OFFSET 1792
|
||||
#define R600_WB_IH_WPTR_OFFSET 2048
|
||||
#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
|
||||
#define R600_WB_EVENT_OFFSET 3072
|
||||
|
||||
/**
|
||||
|
|
|
@ -947,6 +947,15 @@ static struct radeon_asic r600_asic = {
|
|||
.ring_test = &r600_ring_test,
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &r600_gpu_is_lockup,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &r600_dma_ring_ib_execute,
|
||||
.emit_fence = &r600_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
|
@ -963,10 +972,10 @@ static struct radeon_asic r600_asic = {
|
|||
.copy = {
|
||||
.blit = &r600_copy_blit,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = &r600_copy_blit,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &r600_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &r600_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
@ -1022,6 +1031,15 @@ static struct radeon_asic rs780_asic = {
|
|||
.ring_test = &r600_ring_test,
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &r600_gpu_is_lockup,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &r600_dma_ring_ib_execute,
|
||||
.emit_fence = &r600_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
|
@ -1038,10 +1056,10 @@ static struct radeon_asic rs780_asic = {
|
|||
.copy = {
|
||||
.blit = &r600_copy_blit,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = &r600_copy_blit,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &r600_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &r600_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
@ -1097,6 +1115,15 @@ static struct radeon_asic rv770_asic = {
|
|||
.ring_test = &r600_ring_test,
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &r600_gpu_is_lockup,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &r600_dma_ring_ib_execute,
|
||||
.emit_fence = &r600_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
|
@ -1113,10 +1140,10 @@ static struct radeon_asic rv770_asic = {
|
|||
.copy = {
|
||||
.blit = &r600_copy_blit,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = &r600_copy_blit,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &r600_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &r600_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
@ -1172,6 +1199,15 @@ static struct radeon_asic evergreen_asic = {
|
|||
.ring_test = &r600_ring_test,
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &evergreen_gpu_is_lockup,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &evergreen_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
|
@ -1188,10 +1224,10 @@ static struct radeon_asic evergreen_asic = {
|
|||
.copy = {
|
||||
.blit = &r600_copy_blit,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = &r600_copy_blit,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &evergreen_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &evergreen_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
@ -1248,6 +1284,15 @@ static struct radeon_asic sumo_asic = {
|
|||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &evergreen_gpu_is_lockup,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &evergreen_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
.set = &evergreen_irq_set,
|
||||
|
@ -1263,10 +1308,10 @@ static struct radeon_asic sumo_asic = {
|
|||
.copy = {
|
||||
.blit = &r600_copy_blit,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = &r600_copy_blit,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &evergreen_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &evergreen_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
@ -1322,6 +1367,15 @@ static struct radeon_asic btc_asic = {
|
|||
.ring_test = &r600_ring_test,
|
||||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &evergreen_gpu_is_lockup,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &evergreen_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &r600_dma_is_lockup,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
|
@ -1338,10 +1392,10 @@ static struct radeon_asic btc_asic = {
|
|||
.copy = {
|
||||
.blit = &r600_copy_blit,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = &r600_copy_blit,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &evergreen_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &evergreen_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
@ -1391,7 +1445,7 @@ static struct radeon_asic cayman_asic = {
|
|||
.vm = {
|
||||
.init = &cayman_vm_init,
|
||||
.fini = &cayman_vm_fini,
|
||||
.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.set_page = &cayman_vm_set_page,
|
||||
},
|
||||
.ring = {
|
||||
|
@ -1427,6 +1481,26 @@ static struct radeon_asic cayman_asic = {
|
|||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &evergreen_gpu_is_lockup,
|
||||
.vm_flush = &cayman_vm_flush,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
.vm_flush = &cayman_dma_vm_flush,
|
||||
},
|
||||
[CAYMAN_RING_TYPE_DMA1_INDEX] = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
.vm_flush = &cayman_dma_vm_flush,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
|
@ -1443,10 +1517,10 @@ static struct radeon_asic cayman_asic = {
|
|||
.copy = {
|
||||
.blit = &r600_copy_blit,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = &r600_copy_blit,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &evergreen_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &evergreen_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
@ -1496,7 +1570,7 @@ static struct radeon_asic trinity_asic = {
|
|||
.vm = {
|
||||
.init = &cayman_vm_init,
|
||||
.fini = &cayman_vm_fini,
|
||||
.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.set_page = &cayman_vm_set_page,
|
||||
},
|
||||
.ring = {
|
||||
|
@ -1532,6 +1606,26 @@ static struct radeon_asic trinity_asic = {
|
|||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &evergreen_gpu_is_lockup,
|
||||
.vm_flush = &cayman_vm_flush,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
.vm_flush = &cayman_dma_vm_flush,
|
||||
},
|
||||
[CAYMAN_RING_TYPE_DMA1_INDEX] = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
.vm_flush = &cayman_dma_vm_flush,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
|
@ -1548,10 +1642,10 @@ static struct radeon_asic trinity_asic = {
|
|||
.copy = {
|
||||
.blit = &r600_copy_blit,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = &r600_copy_blit,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &evergreen_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &evergreen_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
@ -1601,7 +1695,7 @@ static struct radeon_asic si_asic = {
|
|||
.vm = {
|
||||
.init = &si_vm_init,
|
||||
.fini = &si_vm_fini,
|
||||
.pt_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.pt_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.set_page = &si_vm_set_page,
|
||||
},
|
||||
.ring = {
|
||||
|
@ -1637,6 +1731,26 @@ static struct radeon_asic si_asic = {
|
|||
.ib_test = &r600_ib_test,
|
||||
.is_lockup = &si_gpu_is_lockup,
|
||||
.vm_flush = &si_vm_flush,
|
||||
},
|
||||
[R600_RING_TYPE_DMA_INDEX] = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
.vm_flush = &si_dma_vm_flush,
|
||||
},
|
||||
[CAYMAN_RING_TYPE_DMA1_INDEX] = {
|
||||
.ib_execute = &cayman_dma_ring_ib_execute,
|
||||
.emit_fence = &evergreen_dma_fence_ring_emit,
|
||||
.emit_semaphore = &r600_dma_semaphore_ring_emit,
|
||||
.cs_parse = NULL,
|
||||
.ring_test = &r600_dma_ring_test,
|
||||
.ib_test = &r600_dma_ib_test,
|
||||
.is_lockup = &cayman_dma_is_lockup,
|
||||
.vm_flush = &si_dma_vm_flush,
|
||||
}
|
||||
},
|
||||
.irq = {
|
||||
|
@ -1653,10 +1767,10 @@ static struct radeon_asic si_asic = {
|
|||
.copy = {
|
||||
.blit = NULL,
|
||||
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = NULL,
|
||||
.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.copy = NULL,
|
||||
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
|
||||
.dma = &si_copy_dma,
|
||||
.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
.copy = &si_copy_dma,
|
||||
.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
|
||||
},
|
||||
.surface = {
|
||||
.set_reg = r600_set_surface_reg,
|
||||
|
|
|
@ -309,6 +309,14 @@ void r600_semaphore_ring_emit(struct radeon_device *rdev,
|
|||
struct radeon_ring *cp,
|
||||
struct radeon_semaphore *semaphore,
|
||||
bool emit_wait);
|
||||
void r600_dma_fence_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_fence *fence);
|
||||
void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring,
|
||||
struct radeon_semaphore *semaphore,
|
||||
bool emit_wait);
|
||||
void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||
bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||
bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
int r600_asic_reset(struct radeon_device *rdev);
|
||||
int r600_set_surface_reg(struct radeon_device *rdev, int reg,
|
||||
|
@ -316,11 +324,16 @@ int r600_set_surface_reg(struct radeon_device *rdev, int reg,
|
|||
uint32_t offset, uint32_t obj_size);
|
||||
void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
|
||||
int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||
int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||
void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||
int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
|
||||
int r600_copy_blit(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_gpu_pages, struct radeon_fence **fence);
|
||||
int r600_copy_dma(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_gpu_pages, struct radeon_fence **fence);
|
||||
void r600_hpd_init(struct radeon_device *rdev);
|
||||
void r600_hpd_fini(struct radeon_device *rdev);
|
||||
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
|
||||
|
@ -428,6 +441,14 @@ extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
|
|||
void evergreen_disable_interrupt_state(struct radeon_device *rdev);
|
||||
int evergreen_blit_init(struct radeon_device *rdev);
|
||||
int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
|
||||
void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
|
||||
struct radeon_fence *fence);
|
||||
void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
|
||||
struct radeon_ib *ib);
|
||||
int evergreen_copy_dma(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_gpu_pages,
|
||||
struct radeon_fence **fence);
|
||||
|
||||
/*
|
||||
* cayman
|
||||
|
@ -449,6 +470,10 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
|
|||
uint64_t addr, unsigned count,
|
||||
uint32_t incr, uint32_t flags);
|
||||
int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||
void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
|
||||
struct radeon_ib *ib);
|
||||
bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
|
||||
void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
|
||||
|
||||
/* DCE6 - SI */
|
||||
void dce6_bandwidth_update(struct radeon_device *rdev);
|
||||
|
@ -476,5 +501,10 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
|
|||
void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
|
||||
int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
|
||||
uint64_t si_get_gpu_clock(struct radeon_device *rdev);
|
||||
int si_copy_dma(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_gpu_pages,
|
||||
struct radeon_fence **fence);
|
||||
void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -26,16 +26,31 @@
|
|||
#include "radeon_reg.h"
|
||||
#include "radeon.h"
|
||||
|
||||
#define RADEON_TEST_COPY_BLIT 1
|
||||
#define RADEON_TEST_COPY_DMA 0
|
||||
|
||||
|
||||
/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
|
||||
void radeon_test_moves(struct radeon_device *rdev)
|
||||
static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
|
||||
{
|
||||
struct radeon_bo *vram_obj = NULL;
|
||||
struct radeon_bo **gtt_obj = NULL;
|
||||
struct radeon_fence *fence = NULL;
|
||||
uint64_t gtt_addr, vram_addr;
|
||||
unsigned i, n, size;
|
||||
int r;
|
||||
int r, ring;
|
||||
|
||||
switch (flag) {
|
||||
case RADEON_TEST_COPY_DMA:
|
||||
ring = radeon_copy_dma_ring_index(rdev);
|
||||
break;
|
||||
case RADEON_TEST_COPY_BLIT:
|
||||
ring = radeon_copy_blit_ring_index(rdev);
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Unknown copy method\n");
|
||||
return;
|
||||
}
|
||||
|
||||
size = 1024 * 1024;
|
||||
|
||||
|
@ -106,7 +121,10 @@ void radeon_test_moves(struct radeon_device *rdev)
|
|||
|
||||
radeon_bo_kunmap(gtt_obj[i]);
|
||||
|
||||
r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
|
||||
if (ring == R600_RING_TYPE_DMA_INDEX)
|
||||
r = radeon_copy_dma(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
|
||||
else
|
||||
r = radeon_copy_blit(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
|
||||
goto out_cleanup;
|
||||
|
@ -149,7 +167,10 @@ void radeon_test_moves(struct radeon_device *rdev)
|
|||
|
||||
radeon_bo_kunmap(vram_obj);
|
||||
|
||||
r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
|
||||
if (ring == R600_RING_TYPE_DMA_INDEX)
|
||||
r = radeon_copy_dma(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
|
||||
else
|
||||
r = radeon_copy_blit(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
|
||||
goto out_cleanup;
|
||||
|
@ -223,6 +244,14 @@ void radeon_test_moves(struct radeon_device *rdev)
|
|||
}
|
||||
}
|
||||
|
||||
void radeon_test_moves(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->asic->copy.dma)
|
||||
radeon_do_test_moves(rdev, RADEON_TEST_COPY_DMA);
|
||||
if (rdev->asic->copy.blit)
|
||||
radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT);
|
||||
}
|
||||
|
||||
void radeon_test_ring_sync(struct radeon_device *rdev,
|
||||
struct radeon_ring *ringA,
|
||||
struct radeon_ring *ringB)
|
||||
|
|
|
@ -316,6 +316,7 @@ void r700_cp_stop(struct radeon_device *rdev)
|
|||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
|
||||
WREG32(SCRATCH_UMSK, 0);
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
||||
}
|
||||
|
||||
static int rv770_cp_load_microcode(struct radeon_device *rdev)
|
||||
|
@ -583,6 +584,8 @@ static void rv770_gpu_init(struct radeon_device *rdev)
|
|||
WREG32(GB_TILING_CONFIG, gb_tiling_config);
|
||||
WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
||||
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
||||
WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
|
||||
WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
|
||||
|
||||
WREG32(CGTS_SYS_TCC_DISABLE, 0);
|
||||
WREG32(CGTS_TCC_DISABLE, 0);
|
||||
|
@ -886,7 +889,7 @@ static int rv770_mc_init(struct radeon_device *rdev)
|
|||
|
||||
static int rv770_startup(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
struct radeon_ring *ring;
|
||||
int r;
|
||||
|
||||
/* enable pcie gen2 link */
|
||||
|
@ -932,6 +935,12 @@ static int rv770_startup(struct radeon_device *rdev)
|
|||
return r;
|
||||
}
|
||||
|
||||
r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
r = r600_irq_init(rdev);
|
||||
if (r) {
|
||||
|
@ -941,11 +950,20 @@ static int rv770_startup(struct radeon_device *rdev)
|
|||
}
|
||||
r600_irq_set(rdev);
|
||||
|
||||
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
|
||||
R600_CP_RB_RPTR, R600_CP_RB_WPTR,
|
||||
0, 0xfffff, RADEON_CP_PACKET2);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
|
||||
DMA_RB_RPTR, DMA_RB_WPTR,
|
||||
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = rv770_cp_load_microcode(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
@ -953,6 +971,10 @@ static int rv770_startup(struct radeon_device *rdev)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
r = r600_dma_resume(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_ib_pool_init(rdev);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
||||
|
@ -995,7 +1017,7 @@ int rv770_suspend(struct radeon_device *rdev)
|
|||
{
|
||||
r600_audio_fini(rdev);
|
||||
r700_cp_stop(rdev);
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
||||
r600_dma_stop(rdev);
|
||||
r600_irq_suspend(rdev);
|
||||
radeon_wb_disable(rdev);
|
||||
rv770_pcie_gart_disable(rdev);
|
||||
|
@ -1066,6 +1088,9 @@ int rv770_init(struct radeon_device *rdev)
|
|||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
|
||||
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
|
||||
|
||||
rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
|
||||
r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
|
||||
|
||||
rdev->ih.ring_obj = NULL;
|
||||
r600_ih_ring_init(rdev, 64 * 1024);
|
||||
|
||||
|
@ -1078,6 +1103,7 @@ int rv770_init(struct radeon_device *rdev)
|
|||
if (r) {
|
||||
dev_err(rdev->dev, "disabling GPU acceleration\n");
|
||||
r700_cp_fini(rdev);
|
||||
r600_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
radeon_wb_fini(rdev);
|
||||
radeon_ib_pool_fini(rdev);
|
||||
|
@ -1093,6 +1119,7 @@ void rv770_fini(struct radeon_device *rdev)
|
|||
{
|
||||
r600_blit_fini(rdev);
|
||||
r700_cp_fini(rdev);
|
||||
r600_dma_fini(rdev);
|
||||
r600_irq_fini(rdev);
|
||||
radeon_wb_fini(rdev);
|
||||
radeon_ib_pool_fini(rdev);
|
||||
|
|
|
@ -109,6 +109,9 @@
|
|||
#define PIPE_TILING__SHIFT 1
|
||||
#define PIPE_TILING__MASK 0x0000000e
|
||||
|
||||
#define DMA_TILING_CONFIG 0x3ec8
|
||||
#define DMA_TILING_CONFIG2 0xd0b8
|
||||
|
||||
#define GC_USER_SHADER_PIPE_CONFIG 0x8954
|
||||
#define INACTIVE_QD_PIPES(x) ((x) << 8)
|
||||
#define INACTIVE_QD_PIPES_MASK 0x0000FF00
|
||||
|
@ -358,6 +361,26 @@
|
|||
|
||||
#define WAIT_UNTIL 0x8040
|
||||
|
||||
/* async DMA */
|
||||
#define DMA_RB_RPTR 0xd008
|
||||
#define DMA_RB_WPTR 0xd00c
|
||||
|
||||
/* async DMA packets */
|
||||
#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
|
||||
(((t) & 0x1) << 23) | \
|
||||
(((s) & 0x1) << 22) | \
|
||||
(((n) & 0xFFFF) << 0))
|
||||
/* async DMA Packet types */
|
||||
#define DMA_PACKET_WRITE 0x2
|
||||
#define DMA_PACKET_COPY 0x3
|
||||
#define DMA_PACKET_INDIRECT_BUFFER 0x4
|
||||
#define DMA_PACKET_SEMAPHORE 0x5
|
||||
#define DMA_PACKET_FENCE 0x6
|
||||
#define DMA_PACKET_TRAP 0x7
|
||||
#define DMA_PACKET_CONSTANT_FILL 0xd
|
||||
#define DMA_PACKET_NOP 0xf
|
||||
|
||||
|
||||
#define SRBM_STATUS 0x0E50
|
||||
|
||||
/* DCE 3.2 HDMI */
|
||||
|
|
|
@ -1660,6 +1660,8 @@ static void si_gpu_init(struct radeon_device *rdev)
|
|||
WREG32(GB_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
|
||||
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
|
||||
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
|
||||
|
||||
si_tiling_mode_table_init(rdev);
|
||||
|
||||
|
@ -1836,6 +1838,9 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable)
|
|||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
|
||||
WREG32(SCRATCH_UMSK, 0);
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
||||
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
|
||||
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
|
||||
}
|
||||
udelay(50);
|
||||
}
|
||||
|
@ -2820,30 +2825,86 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
|
|||
{
|
||||
struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
|
||||
uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
|
||||
uint64_t value;
|
||||
unsigned ndw;
|
||||
|
||||
while (count) {
|
||||
unsigned ndw = 2 + count * 2;
|
||||
if (ndw > 0x3FFE)
|
||||
ndw = 0x3FFE;
|
||||
if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
|
||||
while (count) {
|
||||
ndw = 2 + count * 2;
|
||||
if (ndw > 0x3FFE)
|
||||
ndw = 0x3FFE;
|
||||
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
|
||||
WRITE_DATA_DST_SEL(1)));
|
||||
radeon_ring_write(ring, pe);
|
||||
radeon_ring_write(ring, upper_32_bits(pe));
|
||||
for (; ndw > 2; ndw -= 2, --count, pe += 8) {
|
||||
uint64_t value;
|
||||
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
||||
value = radeon_vm_map_gart(rdev, addr);
|
||||
value &= 0xFFFFFFFFFFFFF000ULL;
|
||||
} else if (flags & RADEON_VM_PAGE_VALID)
|
||||
value = addr;
|
||||
else
|
||||
value = 0;
|
||||
addr += incr;
|
||||
value |= r600_flags;
|
||||
radeon_ring_write(ring, value);
|
||||
radeon_ring_write(ring, upper_32_bits(value));
|
||||
radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
|
||||
radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
|
||||
WRITE_DATA_DST_SEL(1)));
|
||||
radeon_ring_write(ring, pe);
|
||||
radeon_ring_write(ring, upper_32_bits(pe));
|
||||
for (; ndw > 2; ndw -= 2, --count, pe += 8) {
|
||||
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
||||
value = radeon_vm_map_gart(rdev, addr);
|
||||
value &= 0xFFFFFFFFFFFFF000ULL;
|
||||
} else if (flags & RADEON_VM_PAGE_VALID) {
|
||||
value = addr;
|
||||
} else {
|
||||
value = 0;
|
||||
}
|
||||
addr += incr;
|
||||
value |= r600_flags;
|
||||
radeon_ring_write(ring, value);
|
||||
radeon_ring_write(ring, upper_32_bits(value));
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* DMA */
|
||||
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
||||
while (count) {
|
||||
ndw = count * 2;
|
||||
if (ndw > 0xFFFFE)
|
||||
ndw = 0xFFFFE;
|
||||
|
||||
/* for non-physically contiguous pages (system) */
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw));
|
||||
radeon_ring_write(ring, pe);
|
||||
radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
|
||||
for (; ndw > 0; ndw -= 2, --count, pe += 8) {
|
||||
if (flags & RADEON_VM_PAGE_SYSTEM) {
|
||||
value = radeon_vm_map_gart(rdev, addr);
|
||||
value &= 0xFFFFFFFFFFFFF000ULL;
|
||||
} else if (flags & RADEON_VM_PAGE_VALID) {
|
||||
value = addr;
|
||||
} else {
|
||||
value = 0;
|
||||
}
|
||||
addr += incr;
|
||||
value |= r600_flags;
|
||||
radeon_ring_write(ring, value);
|
||||
radeon_ring_write(ring, upper_32_bits(value));
|
||||
}
|
||||
}
|
||||
} else {
|
||||
while (count) {
|
||||
ndw = count * 2;
|
||||
if (ndw > 0xFFFFE)
|
||||
ndw = 0xFFFFE;
|
||||
|
||||
if (flags & RADEON_VM_PAGE_VALID)
|
||||
value = addr;
|
||||
else
|
||||
value = 0;
|
||||
/* for physically contiguous pages (vram) */
|
||||
radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw));
|
||||
radeon_ring_write(ring, pe); /* dst addr */
|
||||
radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
|
||||
radeon_ring_write(ring, r600_flags); /* mask */
|
||||
radeon_ring_write(ring, 0);
|
||||
radeon_ring_write(ring, value); /* value */
|
||||
radeon_ring_write(ring, upper_32_bits(value));
|
||||
radeon_ring_write(ring, incr); /* increment size */
|
||||
radeon_ring_write(ring, 0);
|
||||
pe += ndw * 4;
|
||||
addr += (ndw / 2) * incr;
|
||||
count -= ndw / 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -2891,6 +2952,32 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
|||
radeon_ring_write(ring, 0x0);
|
||||
}
|
||||
|
||||
void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[ridx];
|
||||
|
||||
if (vm == NULL)
|
||||
return;
|
||||
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
|
||||
if (vm->id < 8) {
|
||||
radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
|
||||
} else {
|
||||
radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2));
|
||||
}
|
||||
radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
|
||||
|
||||
/* flush hdp cache */
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
|
||||
radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
|
||||
radeon_ring_write(ring, 1);
|
||||
|
||||
/* bits 0-7 are the VM contexts0-7 */
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
|
||||
radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
|
||||
radeon_ring_write(ring, 1 << vm->id);
|
||||
}
|
||||
|
||||
/*
|
||||
* RLC
|
||||
*/
|
||||
|
@ -3059,6 +3146,10 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
|
|||
WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
|
||||
WREG32(CP_INT_CNTL_RING1, 0);
|
||||
WREG32(CP_INT_CNTL_RING2, 0);
|
||||
tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
|
||||
WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
|
||||
tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
|
||||
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
|
||||
WREG32(GRBM_INT_CNTL, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
||||
|
@ -3178,6 +3269,7 @@ int si_irq_set(struct radeon_device *rdev)
|
|||
u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
|
||||
u32 grbm_int_cntl = 0;
|
||||
u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
|
||||
u32 dma_cntl, dma_cntl1;
|
||||
|
||||
if (!rdev->irq.installed) {
|
||||
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
|
||||
|
@ -3198,6 +3290,9 @@ int si_irq_set(struct radeon_device *rdev)
|
|||
hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
|
||||
hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
|
||||
|
||||
dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
|
||||
dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
|
||||
|
||||
/* enable CP interrupts on all rings */
|
||||
if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
|
||||
DRM_DEBUG("si_irq_set: sw int gfx\n");
|
||||
|
@ -3211,6 +3306,15 @@ int si_irq_set(struct radeon_device *rdev)
|
|||
DRM_DEBUG("si_irq_set: sw int cp2\n");
|
||||
cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
|
||||
}
|
||||
if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
|
||||
DRM_DEBUG("si_irq_set: sw int dma\n");
|
||||
dma_cntl |= TRAP_ENABLE;
|
||||
}
|
||||
|
||||
if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
|
||||
DRM_DEBUG("si_irq_set: sw int dma1\n");
|
||||
dma_cntl1 |= TRAP_ENABLE;
|
||||
}
|
||||
if (rdev->irq.crtc_vblank_int[0] ||
|
||||
atomic_read(&rdev->irq.pflip[0])) {
|
||||
DRM_DEBUG("si_irq_set: vblank 0\n");
|
||||
|
@ -3270,6 +3374,9 @@ int si_irq_set(struct radeon_device *rdev)
|
|||
WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
|
||||
WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
|
||||
|
||||
WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
|
||||
WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
|
||||
|
||||
WREG32(GRBM_INT_CNTL, grbm_int_cntl);
|
||||
|
||||
WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
|
||||
|
@ -3728,9 +3835,17 @@ int si_irq_process(struct radeon_device *rdev)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case 224: /* DMA trap event */
|
||||
DRM_DEBUG("IH: DMA trap\n");
|
||||
radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
|
||||
break;
|
||||
case 233: /* GUI IDLE */
|
||||
DRM_DEBUG("IH: GUI idle\n");
|
||||
break;
|
||||
case 244: /* DMA trap event */
|
||||
DRM_DEBUG("IH: DMA1 trap\n");
|
||||
radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
|
||||
break;
|
||||
default:
|
||||
DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
|
||||
break;
|
||||
|
@ -3754,6 +3869,80 @@ int si_irq_process(struct radeon_device *rdev)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/**
|
||||
* si_copy_dma - copy pages using the DMA engine
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @src_offset: src GPU address
|
||||
* @dst_offset: dst GPU address
|
||||
* @num_gpu_pages: number of GPU pages to xfer
|
||||
* @fence: radeon fence object
|
||||
*
|
||||
* Copy GPU paging using the DMA engine (SI).
|
||||
* Used by the radeon ttm implementation to move pages if
|
||||
* registered as the asic copy callback.
|
||||
*/
|
||||
int si_copy_dma(struct radeon_device *rdev,
|
||||
uint64_t src_offset, uint64_t dst_offset,
|
||||
unsigned num_gpu_pages,
|
||||
struct radeon_fence **fence)
|
||||
{
|
||||
struct radeon_semaphore *sem = NULL;
|
||||
int ring_index = rdev->asic->copy.dma_ring_index;
|
||||
struct radeon_ring *ring = &rdev->ring[ring_index];
|
||||
u32 size_in_bytes, cur_size_in_bytes;
|
||||
int i, num_loops;
|
||||
int r = 0;
|
||||
|
||||
r = radeon_semaphore_create(rdev, &sem);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: moving bo (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
|
||||
num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff);
|
||||
r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: moving bo (%d).\n", r);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
if (radeon_fence_need_sync(*fence, ring->idx)) {
|
||||
radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
|
||||
ring->idx);
|
||||
radeon_fence_note_sync(*fence, ring->idx);
|
||||
} else {
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
}
|
||||
|
||||
for (i = 0; i < num_loops; i++) {
|
||||
cur_size_in_bytes = size_in_bytes;
|
||||
if (cur_size_in_bytes > 0xFFFFF)
|
||||
cur_size_in_bytes = 0xFFFFF;
|
||||
size_in_bytes -= cur_size_in_bytes;
|
||||
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));
|
||||
radeon_ring_write(ring, dst_offset & 0xffffffff);
|
||||
radeon_ring_write(ring, src_offset & 0xffffffff);
|
||||
radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
|
||||
radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
|
||||
src_offset += cur_size_in_bytes;
|
||||
dst_offset += cur_size_in_bytes;
|
||||
}
|
||||
|
||||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
return r;
|
||||
}
|
||||
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, *fence);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/*
|
||||
* startup/shutdown callbacks
|
||||
*/
|
||||
|
@ -3825,6 +4014,18 @@ static int si_startup(struct radeon_device *rdev)
|
|||
return r;
|
||||
}
|
||||
|
||||
r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Enable IRQ */
|
||||
r = si_irq_init(rdev);
|
||||
if (r) {
|
||||
|
@ -3855,6 +4056,22 @@ static int si_startup(struct radeon_device *rdev)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
|
||||
DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
|
||||
DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
|
||||
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
|
||||
r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
|
||||
DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
|
||||
DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
|
||||
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = si_cp_load_microcode(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
@ -3862,6 +4079,10 @@ static int si_startup(struct radeon_device *rdev)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
r = cayman_dma_resume(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_ib_pool_init(rdev);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
||||
|
@ -3903,9 +4124,7 @@ int si_resume(struct radeon_device *rdev)
|
|||
int si_suspend(struct radeon_device *rdev)
|
||||
{
|
||||
si_cp_enable(rdev, false);
|
||||
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
|
||||
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
|
||||
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
|
||||
cayman_dma_stop(rdev);
|
||||
si_irq_suspend(rdev);
|
||||
radeon_wb_disable(rdev);
|
||||
si_pcie_gart_disable(rdev);
|
||||
|
@ -3983,6 +4202,14 @@ int si_init(struct radeon_device *rdev)
|
|||
ring->ring_obj = NULL;
|
||||
r600_ring_init(rdev, ring, 1024 * 1024);
|
||||
|
||||
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
||||
ring->ring_obj = NULL;
|
||||
r600_ring_init(rdev, ring, 64 * 1024);
|
||||
|
||||
ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
|
||||
ring->ring_obj = NULL;
|
||||
r600_ring_init(rdev, ring, 64 * 1024);
|
||||
|
||||
rdev->ih.ring_obj = NULL;
|
||||
r600_ih_ring_init(rdev, 64 * 1024);
|
||||
|
||||
|
@ -3995,6 +4222,7 @@ int si_init(struct radeon_device *rdev)
|
|||
if (r) {
|
||||
dev_err(rdev->dev, "disabling GPU acceleration\n");
|
||||
si_cp_fini(rdev);
|
||||
cayman_dma_fini(rdev);
|
||||
si_irq_fini(rdev);
|
||||
si_rlc_fini(rdev);
|
||||
radeon_wb_fini(rdev);
|
||||
|
@ -4023,6 +4251,7 @@ void si_fini(struct radeon_device *rdev)
|
|||
r600_blit_fini(rdev);
|
||||
#endif
|
||||
si_cp_fini(rdev);
|
||||
cayman_dma_fini(rdev);
|
||||
si_irq_fini(rdev);
|
||||
si_rlc_fini(rdev);
|
||||
radeon_wb_fini(rdev);
|
||||
|
|
|
@ -936,4 +936,61 @@
|
|||
#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
|
||||
#define PACKET3_SWITCH_BUFFER 0x8B
|
||||
|
||||
/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
|
||||
#define DMA0_REGISTER_OFFSET 0x0 /* not a register */
|
||||
#define DMA1_REGISTER_OFFSET 0x800 /* not a register */
|
||||
|
||||
#define DMA_RB_CNTL 0xd000
|
||||
# define DMA_RB_ENABLE (1 << 0)
|
||||
# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
|
||||
# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
|
||||
# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
|
||||
# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
|
||||
# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
|
||||
#define DMA_RB_BASE 0xd004
|
||||
#define DMA_RB_RPTR 0xd008
|
||||
#define DMA_RB_WPTR 0xd00c
|
||||
|
||||
#define DMA_RB_RPTR_ADDR_HI 0xd01c
|
||||
#define DMA_RB_RPTR_ADDR_LO 0xd020
|
||||
|
||||
#define DMA_IB_CNTL 0xd024
|
||||
# define DMA_IB_ENABLE (1 << 0)
|
||||
# define DMA_IB_SWAP_ENABLE (1 << 4)
|
||||
#define DMA_IB_RPTR 0xd028
|
||||
#define DMA_CNTL 0xd02c
|
||||
# define TRAP_ENABLE (1 << 0)
|
||||
# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
|
||||
# define SEM_WAIT_INT_ENABLE (1 << 2)
|
||||
# define DATA_SWAP_ENABLE (1 << 3)
|
||||
# define FENCE_SWAP_ENABLE (1 << 4)
|
||||
# define CTXEMPTY_INT_ENABLE (1 << 28)
|
||||
#define DMA_TILING_CONFIG 0xd0b8
|
||||
|
||||
#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
|
||||
(((b) & 0x1) << 26) | \
|
||||
(((t) & 0x1) << 23) | \
|
||||
(((s) & 0x1) << 22) | \
|
||||
(((n) & 0xFFFFF) << 0))
|
||||
|
||||
#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
|
||||
(((vmid) & 0xF) << 20) | \
|
||||
(((n) & 0xFFFFF) << 0))
|
||||
|
||||
#define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
|
||||
(1 << 26) | \
|
||||
(1 << 21) | \
|
||||
(((n) & 0xFFFFF) << 0))
|
||||
|
||||
/* async DMA Packet types */
|
||||
#define DMA_PACKET_WRITE 0x2
|
||||
#define DMA_PACKET_COPY 0x3
|
||||
#define DMA_PACKET_INDIRECT_BUFFER 0x4
|
||||
#define DMA_PACKET_SEMAPHORE 0x5
|
||||
#define DMA_PACKET_FENCE 0x6
|
||||
#define DMA_PACKET_TRAP 0x7
|
||||
#define DMA_PACKET_SRBM_WRITE 0x9
|
||||
#define DMA_PACKET_CONSTANT_FILL 0xd
|
||||
#define DMA_PACKET_NOP 0xf
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Add table
Reference in a new issue