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sh: prefix sh-specific "CCR" and "CCR2" by "SH_"

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Commit bcf24e1daa ("mmc: omap_hsmmc: use the generic config for
omap2plus devices"), enabled the build for other platforms for compile
testing.

sh-allmodconfig now fails with:

    include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
    make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1

This happens because SuperH #defines "CCR", which is one of the enum
values in include/linux/omap-dma.h.  There's a similar issue with "CCR2"
on sh2a.

As "CCR" and "CCR2" are too generic names for global #defines, prefix
them with "SH_" to fix this.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Geert Uytterhoeven 2014-03-03 15:38:33 -08:00 • committed by Linus Torvalds
parent 15c34a7606
commit a5f6ea29f9
11 changed files with 20 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/sh/include/cpu-sh2/cpu/cache.h
View file

@ -18,7 +18,7 @@
#define SH_CACHE_ASSOC 8 #define SH_CACHE_ASSOC 8
#if defined(CONFIG_CPU_SUBTYPE_SH7619) #if defined(CONFIG_CPU_SUBTYPE_SH7619)
#define CCR 0xffffffec #define SH_CCR 0xffffffec
#define CCR_CACHE_CE 0x01 /* Cache enable */ #define CCR_CACHE_CE 0x01 /* Cache enable */
#define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */ #define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */

4
arch/sh/include/cpu-sh2a/cpu/cache.h
View file

@ -17,8 +17,8 @@
#define SH_CACHE_COMBINED 4 #define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8 #define SH_CACHE_ASSOC 8
#define CCR 0xfffc1000 /* CCR1 */ #define SH_CCR 0xfffc1000 /* CCR1 */
#define CCR2 0xfffc1004 #define SH_CCR2 0xfffc1004
/* /*
* Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not

2
arch/sh/include/cpu-sh3/cpu/cache.h
View file

@ -17,7 +17,7 @@
#define SH_CACHE_COMBINED 4 #define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8 #define SH_CACHE_ASSOC 8
#define CCR 0xffffffec /* Address of Cache Control Register */ #define SH_CCR 0xffffffec /* Address of Cache Control Register */
#define CCR_CACHE_CE 0x01 /* Cache Enable */ #define CCR_CACHE_CE 0x01 /* Cache Enable */
#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ #define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */

2
arch/sh/include/cpu-sh4/cpu/cache.h
View file

@ -17,7 +17,7 @@
#define SH_CACHE_COMBINED 4 #define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8 #define SH_CACHE_ASSOC 8
#define CCR 0xff00001c /* Address of Cache Control Register */ #define SH_CCR 0xff00001c /* Address of Cache Control Register */
#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ #define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */

4
arch/sh/kernel/cpu/init.c
View file

@ -112,7 +112,7 @@ static void cache_init(void)
unsigned long ccr, flags; unsigned long ccr, flags;
jump_to_uncached(); jump_to_uncached();
ccr = __raw_readl(CCR); ccr = __raw_readl(SH_CCR);
/* /*
* At this point we don't know whether the cache is enabled or not - a * At this point we don't know whether the cache is enabled or not - a
@ -189,7 +189,7 @@ static void cache_init(void)
l2_cache_init(); l2_cache_init();
__raw_writel(flags, CCR); __raw_writel(flags, SH_CCR);
back_to_cached(); back_to_cached();
} }
#else #else

2
arch/sh/mm/cache-debugfs.c
View file

@ -36,7 +36,7 @@ static int cache_seq_show(struct seq_file *file, void *iter)
*/ */
jump_to_uncached(); jump_to_uncached();
ccr = __raw_readl(CCR); ccr = __raw_readl(SH_CCR);
if ((ccr & CCR_CACHE_ENABLE) == 0) { if ((ccr & CCR_CACHE_ENABLE) == 0) {
back_to_cached(); back_to_cached();

4
arch/sh/mm/cache-sh2.c
View file

@ -63,9 +63,9 @@ static void sh2__flush_invalidate_region(void *start, int size)
local_irq_save(flags); local_irq_save(flags);
jump_to_uncached(); jump_to_uncached();
ccr = __raw_readl(CCR); ccr = __raw_readl(SH_CCR);
ccr |= CCR_CACHE_INVALIDATE; ccr |= CCR_CACHE_INVALIDATE;
__raw_writel(ccr, CCR); __raw_writel(ccr, SH_CCR);
back_to_cached(); back_to_cached();
local_irq_restore(flags); local_irq_restore(flags);

6
arch/sh/mm/cache-sh2a.c
View file

@ -134,7 +134,8 @@ static void sh2a__flush_invalidate_region(void *start, int size)
/* If there are too many pages then just blow the cache */ /* If there are too many pages then just blow the cache */
if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) { if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
__raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR); __raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE,
SH_CCR);
} else { } else {
for (v = begin; v < end; v += L1_CACHE_BYTES) for (v = begin; v < end; v += L1_CACHE_BYTES)
sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v); sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
@ -167,7 +168,8 @@ static void sh2a_flush_icache_range(void *args)
/* I-Cache invalidate */ /* I-Cache invalidate */
/* If there are too many pages then just blow the cache */ /* If there are too many pages then just blow the cache */
if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
__raw_writel(__raw_readl(CCR) | CCR_ICACHE_INVALIDATE, CCR); __raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE,
SH_CCR);
} else { } else {
for (v = start; v < end; v += L1_CACHE_BYTES) for (v = start; v < end; v += L1_CACHE_BYTES)
sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v); sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);

4
arch/sh/mm/cache-sh4.c
View file

@ -133,9 +133,9 @@ static void flush_icache_all(void)
jump_to_uncached(); jump_to_uncached();
/* Flush I-cache */ /* Flush I-cache */
ccr = __raw_readl(CCR); ccr = __raw_readl(SH_CCR);
ccr |= CCR_CACHE_ICI; ccr |= CCR_CACHE_ICI;
__raw_writel(ccr, CCR); __raw_writel(ccr, SH_CCR);
/* /*
* back_to_cached() will take care of the barrier for us, don't add * back_to_cached() will take care of the barrier for us, don't add

4
arch/sh/mm/cache-shx3.c
View file

@ -19,7 +19,7 @@ void __init shx3_cache_init(void)
{ {
unsigned int ccr; unsigned int ccr;
ccr = __raw_readl(CCR); ccr = __raw_readl(SH_CCR);
/* /*
* If we've got cache aliases, resolve them in hardware. * If we've got cache aliases, resolve them in hardware.
@ -40,5 +40,5 @@ void __init shx3_cache_init(void)
ccr |= CCR_CACHE_IBE; ccr |= CCR_CACHE_IBE;
#endif #endif
writel_uncached(ccr, CCR); writel_uncached(ccr, SH_CCR);
} }

4
arch/sh/mm/cache.c
View file

@ -285,8 +285,8 @@ void __init cpu_cache_init(void)
{ {
unsigned int cache_disabled = 0; unsigned int cache_disabled = 0;
#ifdef CCR #ifdef SH_CCR
cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE); cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
#endif #endif
compute_alias(&boot_cpu_data.icache); compute_alias(&boot_cpu_data.icache);