fix the broken annotations in fsldma
a) every bitwise declaration will give a unique type; use typedefs. b) no need to bother with the stuff pointed to by iomem pointers, unless it's accessed directly. noderef will force us to use helpers anyway. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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1 changed files with 27 additions and 20 deletions
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@ -75,12 +75,15 @@
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#define FSL_DMA_DGSR_EOSI 0x02
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#define FSL_DMA_DGSR_EOSI 0x02
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#define FSL_DMA_DGSR_EOLSI 0x01
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#define FSL_DMA_DGSR_EOLSI 0x01
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typedef u64 __bitwise v64;
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typedef u32 __bitwise v32;
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struct fsl_dma_ld_hw {
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struct fsl_dma_ld_hw {
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u64 __bitwise src_addr;
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v64 src_addr;
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u64 __bitwise dst_addr;
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v64 dst_addr;
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u64 __bitwise next_ln_addr;
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v64 next_ln_addr;
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u32 __bitwise count;
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v32 count;
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u32 __bitwise reserve;
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v32 reserve;
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} __attribute__((aligned(32)));
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} __attribute__((aligned(32)));
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struct fsl_desc_sw {
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struct fsl_desc_sw {
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@ -92,13 +95,13 @@ struct fsl_desc_sw {
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} __attribute__((aligned(32)));
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} __attribute__((aligned(32)));
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struct fsl_dma_chan_regs {
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struct fsl_dma_chan_regs {
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u32 __bitwise mr; /* 0x00 - Mode Register */
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u32 mr; /* 0x00 - Mode Register */
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u32 __bitwise sr; /* 0x04 - Status Register */
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u32 sr; /* 0x04 - Status Register */
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u64 __bitwise cdar; /* 0x08 - Current descriptor address register */
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u64 cdar; /* 0x08 - Current descriptor address register */
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u64 __bitwise sar; /* 0x10 - Source Address Register */
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u64 sar; /* 0x10 - Source Address Register */
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u64 __bitwise dar; /* 0x18 - Destination Address Register */
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u64 dar; /* 0x18 - Destination Address Register */
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u32 __bitwise bcr; /* 0x20 - Byte Count Register */
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u32 bcr; /* 0x20 - Byte Count Register */
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u64 __bitwise ndar; /* 0x24 - Next Descriptor Address Register */
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u64 ndar; /* 0x24 - Next Descriptor Address Register */
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};
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};
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struct fsl_dma_chan;
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struct fsl_dma_chan;
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@ -151,25 +154,27 @@ struct fsl_dma_chan {
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#ifndef __powerpc64__
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#ifndef __powerpc64__
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static u64 in_be64(const u64 __iomem *addr)
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static u64 in_be64(const u64 __iomem *addr)
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{
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{
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return ((u64)in_be32((u32 *)addr) << 32) | (in_be32((u32 *)addr + 1));
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return ((u64)in_be32((u32 __iomem *)addr) << 32) |
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(in_be32((u32 __iomem *)addr + 1));
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}
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}
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static void out_be64(u64 __iomem *addr, u64 val)
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static void out_be64(u64 __iomem *addr, u64 val)
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{
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{
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out_be32((u32 *)addr, val >> 32);
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out_be32((u32 __iomem *)addr, val >> 32);
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out_be32((u32 *)addr + 1, (u32)val);
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out_be32((u32 __iomem *)addr + 1, (u32)val);
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}
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}
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/* There is no asm instructions for 64 bits reverse loads and stores */
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/* There is no asm instructions for 64 bits reverse loads and stores */
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static u64 in_le64(const u64 __iomem *addr)
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static u64 in_le64(const u64 __iomem *addr)
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{
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{
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return ((u64)in_le32((u32 *)addr + 1) << 32) | (in_le32((u32 *)addr));
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return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
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(in_le32((u32 __iomem *)addr));
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}
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}
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static void out_le64(u64 __iomem *addr, u64 val)
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static void out_le64(u64 __iomem *addr, u64 val)
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{
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{
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out_le32((u32 *)addr + 1, val >> 32);
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out_le32((u32 __iomem *)addr + 1, val >> 32);
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out_le32((u32 *)addr, (u32)val);
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out_le32((u32 __iomem *)addr, (u32)val);
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}
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}
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#endif
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#endif
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@ -182,9 +187,11 @@ static void out_le64(u64 __iomem *addr, u64 val)
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#define DMA_TO_CPU(fsl_chan, d, width) \
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#define DMA_TO_CPU(fsl_chan, d, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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be##width##_to_cpu(d) : le##width##_to_cpu(d))
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be##width##_to_cpu((__force __be##width)(v##width)d) : \
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le##width##_to_cpu((__force __le##width)(v##width)d))
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#define CPU_TO_DMA(fsl_chan, c, width) \
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#define CPU_TO_DMA(fsl_chan, c, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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cpu_to_be##width(c) : cpu_to_le##width(c))
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(__force v##width)cpu_to_be##width(c) : \
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(__force v##width)cpu_to_le##width(c))
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#endif /* __DMA_FSLDMA_H */
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#endif /* __DMA_FSLDMA_H */
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