EXYNOS4X12: Add support cpufreq for EXYNOS4X12
This patch adds support cpufreq for EXYNOS4X12 SoCs. Basically, the exynos-cpufreq.c is used commonly and exynos4x12-cpufreq.c is used for EXYNOS4212(two Cortex-A9 cores) and EXYNOS4412(four Cortex-A9 cores) SoCs. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Dave Jones <davej@redhat.com>
This commit is contained in:
Jaecheol Lee
Dave Jones
parent
fd0ef7a058
commit
a35c50510d
5 changed files with 547 additions and 0 deletions
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@ -32,3 +32,4 @@ struct exynos_dvfs_info {
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};
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extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
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extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
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@ -47,6 +47,7 @@ config ARM_EXYNOS_CPUFREQ
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bool "SAMSUNG EXYNOS SoCs"
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depends on ARCH_EXYNOS
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select ARM_EXYNOS4210_CPUFREQ if CPU_EXYNOS4210
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select ARM_EXYNOS4X12_CPUFREQ if (SOC_EXYNOS4212 || SOC_EXYNOS4412)
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default y
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help
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This adds the CPUFreq driver common part for Samsung
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@ -60,3 +61,9 @@ config ARM_EXYNOS4210_CPUFREQ
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help
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This adds the CPUFreq driver for Samsung EXYNOS4210
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SoC (S5PV310 or S5PC210).
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config ARM_EXYNOS4X12_CPUFREQ
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bool "Samsung EXYNOS4X12"
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help
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This adds the CPUFreq driver for Samsung EXYNOS4X12
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SoC (EXYNOS4212 or EXYNOS4412).
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@ -45,6 +45,7 @@ obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o
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obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
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obj-$(CONFIG_ARCH_OMAP2PLUS) += omap-cpufreq.o
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##################################################################################
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@ -254,6 +254,8 @@ static int __init exynos_cpufreq_init(void)
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if (soc_is_exynos4210())
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ret = exynos4210_cpufreq_init(exynos_info);
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else if (soc_is_exynos4212() || soc_is_exynos4412())
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ret = exynos4x12_cpufreq_init(exynos_info);
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else
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pr_err("%s: CPU type not found\n", __func__);
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536
drivers/cpufreq/exynos4x12-cpufreq.c
Normal file
536
drivers/cpufreq/exynos4x12-cpufreq.c
Normal file
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@ -0,0 +1,536 @@
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/*
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* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4X12 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <mach/regs-clock.h>
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#include <mach/cpufreq.h>
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#define CPUFREQ_LEVEL_END (L13 + 1)
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static int max_support_idx;
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static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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struct cpufreq_clkdiv {
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unsigned int index;
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unsigned int clkdiv;
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unsigned int clkdiv1;
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};
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static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
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static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
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{L0, 1500 * 1000},
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{L1, 1400 * 1000},
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{L2, 1300 * 1000},
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{L3, 1200 * 1000},
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{L4, 1100 * 1000},
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{L5, 1000 * 1000},
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{L6, 900 * 1000},
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{L7, 800 * 1000},
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{L8, 700 * 1000},
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{L9, 600 * 1000},
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{L10, 500 * 1000},
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{L11, 400 * 1000},
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{L12, 300 * 1000},
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{L13, 200 * 1000},
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{0, CPUFREQ_TABLE_END},
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};
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static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END];
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static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = {
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/*
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* Clock divider value for following
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* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
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* DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
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*/
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/* ARM L0: 1500 MHz */
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{ 0, 3, 7, 0, 6, 1, 2, 0 },
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/* ARM L1: 1400 MHz */
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{ 0, 3, 7, 0, 6, 1, 2, 0 },
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/* ARM L2: 1300 MHz */
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{ 0, 3, 7, 0, 5, 1, 2, 0 },
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/* ARM L3: 1200 MHz */
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{ 0, 3, 7, 0, 5, 1, 2, 0 },
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/* ARM L4: 1100 MHz */
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{ 0, 3, 6, 0, 4, 1, 2, 0 },
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/* ARM L5: 1000 MHz */
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{ 0, 2, 5, 0, 4, 1, 1, 0 },
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/* ARM L6: 900 MHz */
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{ 0, 2, 5, 0, 3, 1, 1, 0 },
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/* ARM L7: 800 MHz */
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{ 0, 2, 5, 0, 3, 1, 1, 0 },
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/* ARM L8: 700 MHz */
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{ 0, 2, 4, 0, 3, 1, 1, 0 },
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/* ARM L9: 600 MHz */
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{ 0, 2, 4, 0, 3, 1, 1, 0 },
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/* ARM L10: 500 MHz */
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{ 0, 2, 4, 0, 3, 1, 1, 0 },
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/* ARM L11: 400 MHz */
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{ 0, 2, 4, 0, 3, 1, 1, 0 },
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/* ARM L12: 300 MHz */
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{ 0, 2, 4, 0, 2, 1, 1, 0 },
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/* ARM L13: 200 MHz */
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{ 0, 1, 3, 0, 1, 1, 1, 0 },
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};
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static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = {
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/*
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* Clock divider value for following
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* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
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* DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
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*/
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/* ARM L0: 1500 MHz */
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{ 0, 3, 7, 0, 6, 1, 2, 0 },
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/* ARM L1: 1400 MHz */
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{ 0, 3, 7, 0, 6, 1, 2, 0 },
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/* ARM L2: 1300 MHz */
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{ 0, 3, 7, 0, 5, 1, 2, 0 },
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/* ARM L3: 1200 MHz */
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{ 0, 3, 7, 0, 5, 1, 2, 0 },
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/* ARM L4: 1100 MHz */
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{ 0, 3, 6, 0, 4, 1, 2, 0 },
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/* ARM L5: 1000 MHz */
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{ 0, 2, 5, 0, 4, 1, 1, 0 },
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/* ARM L6: 900 MHz */
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{ 0, 2, 5, 0, 3, 1, 1, 0 },
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/* ARM L7: 800 MHz */
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{ 0, 2, 5, 0, 3, 1, 1, 0 },
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/* ARM L8: 700 MHz */
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{ 0, 2, 4, 0, 3, 1, 1, 0 },
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/* ARM L9: 600 MHz */
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{ 0, 2, 4, 0, 3, 1, 1, 0 },
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/* ARM L10: 500 MHz */
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{ 0, 2, 4, 0, 3, 1, 1, 0 },
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/* ARM L11: 400 MHz */
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{ 0, 2, 4, 0, 3, 1, 1, 0 },
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/* ARM L12: 300 MHz */
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{ 0, 2, 4, 0, 2, 1, 1, 0 },
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/* ARM L13: 200 MHz */
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{ 0, 1, 3, 0, 1, 1, 1, 0 },
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};
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static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
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/* Clock divider value for following
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* { DIVCOPY, DIVHPM }
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*/
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/* ARM L0: 1500 MHz */
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{ 6, 0 },
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/* ARM L1: 1400 MHz */
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{ 6, 0 },
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/* ARM L2: 1300 MHz */
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{ 5, 0 },
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/* ARM L3: 1200 MHz */
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{ 5, 0 },
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/* ARM L4: 1100 MHz */
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{ 4, 0 },
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/* ARM L5: 1000 MHz */
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{ 4, 0 },
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/* ARM L6: 900 MHz */
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{ 3, 0 },
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/* ARM L7: 800 MHz */
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{ 3, 0 },
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/* ARM L8: 700 MHz */
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{ 3, 0 },
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/* ARM L9: 600 MHz */
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{ 3, 0 },
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/* ARM L10: 500 MHz */
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{ 3, 0 },
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/* ARM L11: 400 MHz */
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{ 3, 0 },
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/* ARM L12: 300 MHz */
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{ 3, 0 },
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/* ARM L13: 200 MHz */
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{ 3, 0 },
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};
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static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
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/* Clock divider value for following
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* { DIVCOPY, DIVHPM, DIVCORES }
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*/
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/* ARM L0: 1500 MHz */
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{ 6, 0, 7 },
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/* ARM L1: 1400 MHz */
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{ 6, 0, 6 },
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/* ARM L2: 1300 MHz */
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{ 5, 0, 6 },
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/* ARM L3: 1200 MHz */
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{ 5, 0, 5 },
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/* ARM L4: 1100 MHz */
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{ 4, 0, 5 },
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/* ARM L5: 1000 MHz */
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{ 4, 0, 4 },
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/* ARM L6: 900 MHz */
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{ 3, 0, 4 },
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/* ARM L7: 800 MHz */
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{ 3, 0, 3 },
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/* ARM L8: 700 MHz */
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{ 3, 0, 3 },
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/* ARM L9: 600 MHz */
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{ 3, 0, 2 },
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/* ARM L10: 500 MHz */
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{ 3, 0, 2 },
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/* ARM L11: 400 MHz */
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{ 3, 0, 1 },
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/* ARM L12: 300 MHz */
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{ 3, 0, 1 },
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/* ARM L13: 200 MHz */
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{ 3, 0, 0 },
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};
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static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
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/* APLL FOUT L0: 1500 MHz */
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((250 << 16) | (4 << 8) | (0x0)),
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/* APLL FOUT L1: 1400 MHz */
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((175 << 16) | (3 << 8) | (0x0)),
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/* APLL FOUT L2: 1300 MHz */
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((325 << 16) | (6 << 8) | (0x0)),
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/* APLL FOUT L3: 1200 MHz */
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((200 << 16) | (4 << 8) | (0x0)),
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/* APLL FOUT L4: 1100 MHz */
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((275 << 16) | (6 << 8) | (0x0)),
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/* APLL FOUT L5: 1000 MHz */
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((125 << 16) | (3 << 8) | (0x0)),
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/* APLL FOUT L6: 900 MHz */
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((150 << 16) | (4 << 8) | (0x0)),
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/* APLL FOUT L7: 800 MHz */
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((100 << 16) | (3 << 8) | (0x0)),
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/* APLL FOUT L8: 700 MHz */
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((175 << 16) | (3 << 8) | (0x1)),
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/* APLL FOUT L9: 600 MHz */
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((200 << 16) | (4 << 8) | (0x1)),
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/* APLL FOUT L10: 500 MHz */
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((125 << 16) | (3 << 8) | (0x1)),
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/* APLL FOUT L11 400 MHz */
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((100 << 16) | (3 << 8) | (0x1)),
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/* APLL FOUT L12: 300 MHz */
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((200 << 16) | (4 << 8) | (0x2)),
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/* APLL FOUT L13: 200 MHz */
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((100 << 16) | (3 << 8) | (0x2)),
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};
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static const unsigned int asv_voltage_4x12[CPUFREQ_LEVEL_END] = {
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1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
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1000000, 987500, 975000, 950000, 925000, 900000, 900000
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};
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static void exynos4x12_set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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unsigned int stat_cpu1;
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/* Change Divider - CPU0 */
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tmp = exynos4x12_clkdiv_table[div_index].clkdiv;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
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while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
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cpu_relax();
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/* Change Divider - CPU1 */
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tmp = exynos4x12_clkdiv_table[div_index].clkdiv1;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
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if (soc_is_exynos4212())
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stat_cpu1 = 0x11;
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else
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stat_cpu1 = 0x111;
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while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
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cpu_relax();
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}
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static void exynos4x12_set_apll(unsigned int index)
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{
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unsigned int tmp, pdiv;
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/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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cpu_relax();
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tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
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>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* 2. Set APLL Lock time */
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pdiv = ((exynos4x12_apll_pms_table[index] >> 8) & 0x3f);
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__raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
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/* 3. Change PLL PMS values */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
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tmp |= exynos4x12_apll_pms_table[index];
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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/* 4. wait_lock_time */
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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} while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
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/* 5. MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
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tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
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{
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unsigned int old_pm = exynos4x12_apll_pms_table[old_index] >> 8;
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unsigned int new_pm = exynos4x12_apll_pms_table[new_index] >> 8;
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return (old_pm == new_pm) ? 0 : 1;
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}
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static void exynos4x12_set_frequency(unsigned int old_index,
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unsigned int new_index)
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{
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unsigned int tmp;
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if (old_index > new_index) {
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if (!exynos4x12_pms_change(old_index, new_index)) {
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/* 1. Change the system clock divider values */
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exynos4x12_set_clkdiv(new_index);
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/* 2. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the system clock divider values */
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exynos4x12_set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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exynos4x12_set_apll(new_index);
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}
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} else if (old_index < new_index) {
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if (!exynos4x12_pms_change(old_index, new_index)) {
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/* 1. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS4_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, EXYNOS4_APLL_CON0);
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/* 2. Change the system clock divider values */
|
||||
exynos4x12_set_clkdiv(new_index);
|
||||
} else {
|
||||
/* Clock Configuration Procedure */
|
||||
/* 1. Change the apll m,p,s value */
|
||||
exynos4x12_set_apll(new_index);
|
||||
/* 2. Change the system clock divider values */
|
||||
exynos4x12_set_clkdiv(new_index);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void __init set_volt_table(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
max_support_idx = L1;
|
||||
|
||||
/* Not supported */
|
||||
exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
|
||||
|
||||
for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
|
||||
exynos4x12_volt_table[i] = asv_voltage_4x12[i];
|
||||
}
|
||||
|
||||
int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
|
||||
{
|
||||
int i;
|
||||
unsigned int tmp;
|
||||
unsigned long rate;
|
||||
|
||||
set_volt_table();
|
||||
|
||||
cpu_clk = clk_get(NULL, "armclk");
|
||||
if (IS_ERR(cpu_clk))
|
||||
return PTR_ERR(cpu_clk);
|
||||
|
||||
moutcore = clk_get(NULL, "moutcore");
|
||||
if (IS_ERR(moutcore))
|
||||
goto err_moutcore;
|
||||
|
||||
mout_mpll = clk_get(NULL, "mout_mpll");
|
||||
if (IS_ERR(mout_mpll))
|
||||
goto err_mout_mpll;
|
||||
|
||||
rate = clk_get_rate(mout_mpll) / 1000;
|
||||
|
||||
mout_apll = clk_get(NULL, "mout_apll");
|
||||
if (IS_ERR(mout_apll))
|
||||
goto err_mout_apll;
|
||||
|
||||
for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
|
||||
|
||||
exynos4x12_clkdiv_table[i].index = i;
|
||||
|
||||
tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
|
||||
|
||||
tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
|
||||
EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
|
||||
EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
|
||||
EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
|
||||
EXYNOS4_CLKDIV_CPU0_ATB_MASK |
|
||||
EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
|
||||
EXYNOS4_CLKDIV_CPU0_APLL_MASK);
|
||||
|
||||
if (soc_is_exynos4212()) {
|
||||
tmp |= ((clkdiv_cpu0_4212[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
|
||||
(clkdiv_cpu0_4212[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
|
||||
(clkdiv_cpu0_4212[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
|
||||
(clkdiv_cpu0_4212[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
|
||||
(clkdiv_cpu0_4212[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
|
||||
(clkdiv_cpu0_4212[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
|
||||
(clkdiv_cpu0_4212[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
|
||||
} else {
|
||||
tmp &= ~EXYNOS4_CLKDIV_CPU0_CORE2_MASK;
|
||||
|
||||
tmp |= ((clkdiv_cpu0_4412[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
|
||||
(clkdiv_cpu0_4412[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
|
||||
(clkdiv_cpu0_4412[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
|
||||
(clkdiv_cpu0_4412[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
|
||||
(clkdiv_cpu0_4412[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
|
||||
(clkdiv_cpu0_4412[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
|
||||
(clkdiv_cpu0_4412[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
|
||||
(clkdiv_cpu0_4412[i][7] << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
|
||||
}
|
||||
|
||||
exynos4x12_clkdiv_table[i].clkdiv = tmp;
|
||||
|
||||
tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
|
||||
|
||||
if (soc_is_exynos4212()) {
|
||||
tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
|
||||
EXYNOS4_CLKDIV_CPU1_HPM_MASK);
|
||||
tmp |= ((clkdiv_cpu1_4212[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
|
||||
(clkdiv_cpu1_4212[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT));
|
||||
} else {
|
||||
tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
|
||||
EXYNOS4_CLKDIV_CPU1_HPM_MASK |
|
||||
EXYNOS4_CLKDIV_CPU1_CORES_MASK);
|
||||
tmp |= ((clkdiv_cpu1_4412[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
|
||||
(clkdiv_cpu1_4412[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
|
||||
(clkdiv_cpu1_4412[i][2] << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT));
|
||||
}
|
||||
exynos4x12_clkdiv_table[i].clkdiv1 = tmp;
|
||||
}
|
||||
|
||||
info->mpll_freq_khz = rate;
|
||||
info->pm_lock_idx = L5;
|
||||
info->pll_safe_idx = L7;
|
||||
info->max_support_idx = max_support_idx;
|
||||
info->min_support_idx = min_support_idx;
|
||||
info->cpu_clk = cpu_clk;
|
||||
info->volt_table = exynos4x12_volt_table;
|
||||
info->freq_table = exynos4x12_freq_table;
|
||||
info->set_freq = exynos4x12_set_frequency;
|
||||
info->need_apll_change = exynos4x12_pms_change;
|
||||
|
||||
return 0;
|
||||
|
||||
err_mout_apll:
|
||||
clk_put(mout_mpll);
|
||||
err_mout_mpll:
|
||||
clk_put(moutcore);
|
||||
err_moutcore:
|
||||
clk_put(cpu_clk);
|
||||
|
||||
pr_debug("%s: failed initialization\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
EXPORT_SYMBOL(exynos4x12_cpufreq_init);
|
||||
Loading…
Reference in a new issue