x86, cacheinfo: Fixup L3 cache information for AMD multi-node processors
L3 cache size, associativity and shared_cpu information need to be adapted to show information for an internal node instead of the entire physical package. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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1 changed files with 22 additions and 10 deletions
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@ -241,7 +241,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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case 0:
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if (!l1->val)
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return;
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assoc = l1->assoc;
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assoc = assocs[l1->assoc];
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line_size = l1->line_size;
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lines_per_tag = l1->lines_per_tag;
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size_in_kb = l1->size_in_kb;
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@ -249,7 +249,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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case 2:
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if (!l2.val)
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return;
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assoc = l2.assoc;
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assoc = assocs[l2.assoc];
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line_size = l2.line_size;
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lines_per_tag = l2.lines_per_tag;
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/* cpu_data has errata corrections for K7 applied */
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@ -258,10 +258,14 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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case 3:
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if (!l3.val)
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return;
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assoc = l3.assoc;
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assoc = assocs[l3.assoc];
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line_size = l3.line_size;
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lines_per_tag = l3.lines_per_tag;
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size_in_kb = l3.size_encoded * 512;
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if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
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size_in_kb = size_in_kb >> 1;
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assoc = assoc >> 1;
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}
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break;
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default:
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return;
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@ -270,18 +274,14 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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eax->split.is_self_initializing = 1;
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eax->split.type = types[leaf];
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eax->split.level = levels[leaf];
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if (leaf == 3)
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eax->split.num_threads_sharing =
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current_cpu_data.x86_max_cores - 1;
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else
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eax->split.num_threads_sharing = 0;
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eax->split.num_threads_sharing = 0;
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eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
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if (assoc == 0xf)
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if (assoc == 0xffff)
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eax->split.is_fully_associative = 1;
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ebx->split.coherency_line_size = line_size - 1;
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ebx->split.ways_of_associativity = assocs[assoc] - 1;
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ebx->split.ways_of_associativity = assoc - 1;
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ebx->split.physical_line_partition = lines_per_tag - 1;
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ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
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(ebx->split.ways_of_associativity + 1) - 1;
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@ -522,6 +522,18 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
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int index_msb, i;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
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struct cpuinfo_x86 *d;
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for_each_online_cpu(i) {
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if (!per_cpu(cpuid4_info, i))
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continue;
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d = &cpu_data(i);
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this_leaf = CPUID4_INFO_IDX(i, index);
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cpumask_copy(to_cpumask(this_leaf->shared_cpu_map),
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d->llc_shared_map);
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}
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return;
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}
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this_leaf = CPUID4_INFO_IDX(cpu, index);
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num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
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