ioat2,3: dynamically resize descriptor ring
Increment the allocation order of the descriptor ring every time we run out of descriptors up to a maximum of allocation order specified by the module parameter 'ioat_max_alloc_order'. After each idle period decrement the allocation order to a minimum order of 'ioat_ring_alloc_order' (i.e. the default ring size, tunable as a module parameter). Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
09c8a5b85e
commit
a309218ace
3 changed files with 187 additions and 31 deletions
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@ -88,6 +88,7 @@ struct ioat_chan_common {
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#define IOAT_RESET_PENDING 2
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struct timer_list timer;
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#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
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#define IDLE_TIMEOUT msecs_to_jiffies(2000)
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#define RESET_DELAY msecs_to_jiffies(100)
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struct ioatdma_device *device;
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dma_addr_t completion_dma;
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@ -43,6 +43,10 @@ static int ioat_ring_alloc_order = 8;
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module_param(ioat_ring_alloc_order, int, 0644);
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MODULE_PARM_DESC(ioat_ring_alloc_order,
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"ioat2+: allocate 2^n descriptors per channel (default: n=8)");
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static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
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module_param(ioat_ring_max_alloc_order, int, 0644);
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MODULE_PARM_DESC(ioat_ring_max_alloc_order,
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"ioat2+: upper limit for dynamic ring resizing (default: n=16)");
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static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
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{
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@ -168,6 +172,7 @@ static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete)
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dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
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__func__);
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clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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}
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}
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@ -253,6 +258,8 @@ static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
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__restart_chan(ioat);
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}
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static bool reshape_ring(struct ioat2_dma_chan *ioat, int order);
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static void ioat2_timer_event(unsigned long data)
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{
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struct ioat2_dma_chan *ioat = (void *) data;
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@ -289,6 +296,23 @@ static void ioat2_timer_event(unsigned long data)
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mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
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}
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spin_unlock_bh(&ioat->ring_lock);
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} else {
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u16 active;
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/* if the ring is idle, empty, and oversized try to step
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* down the size
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*/
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spin_lock_bh(&ioat->ring_lock);
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active = ioat2_ring_active(ioat);
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if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
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reshape_ring(ioat, ioat->alloc_order-1);
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spin_unlock_bh(&ioat->ring_lock);
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/* keep shrinking until we get back to our minimum
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* default size
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*/
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if (ioat->alloc_order > ioat_get_alloc_order())
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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}
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spin_unlock_bh(&chan->cleanup_lock);
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}
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@ -362,7 +386,7 @@ static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
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return cookie;
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}
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static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan)
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static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
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{
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struct ioat_dma_descriptor *hw;
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struct ioat_ring_ent *desc;
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@ -370,12 +394,12 @@ static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan)
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dma_addr_t phys;
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dma = to_ioatdma_device(chan->device);
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hw = pci_pool_alloc(dma->dma_pool, GFP_KERNEL, &phys);
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hw = pci_pool_alloc(dma->dma_pool, flags, &phys);
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if (!hw)
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return NULL;
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memset(hw, 0, sizeof(*hw));
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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desc = kzalloc(sizeof(*desc), flags);
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if (!desc) {
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pci_pool_free(dma->dma_pool, hw, phys);
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return NULL;
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@ -397,6 +421,42 @@ static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *cha
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kfree(desc);
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}
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static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
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{
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struct ioat_ring_ent **ring;
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int descs = 1 << order;
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int i;
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if (order > ioat_get_max_alloc_order())
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return NULL;
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/* allocate the array to hold the software ring */
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ring = kcalloc(descs, sizeof(*ring), flags);
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if (!ring)
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return NULL;
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for (i = 0; i < descs; i++) {
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ring[i] = ioat2_alloc_ring_ent(c, flags);
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if (!ring[i]) {
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while (i--)
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ioat2_free_ring_ent(ring[i], c);
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kfree(ring);
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return NULL;
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}
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set_desc_id(ring[i], i);
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}
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/* link descs */
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for (i = 0; i < descs-1; i++) {
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struct ioat_ring_ent *next = ring[i+1];
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struct ioat_dma_descriptor *hw = ring[i]->hw;
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hw->next = next->txd.phys;
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}
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ring[i]->hw->next = ring[0]->txd.phys;
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return ring;
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}
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/* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
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* @chan: channel to be initialized
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*/
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@ -406,8 +466,7 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c)
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struct ioat_chan_common *chan = &ioat->base;
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struct ioat_ring_ent **ring;
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u32 chanerr;
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int descs;
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int i;
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int order;
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/* have we already been set up? */
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if (ioat->ring)
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@ -435,32 +494,10 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c)
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writel(((u64) chan->completion_dma) >> 32,
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chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
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ioat->alloc_order = ioat_get_alloc_order();
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descs = 1 << ioat->alloc_order;
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/* allocate the array to hold the software ring */
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ring = kcalloc(descs, sizeof(*ring), GFP_KERNEL);
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order = ioat_get_alloc_order();
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ring = ioat2_alloc_ring(c, order, GFP_KERNEL);
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if (!ring)
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return -ENOMEM;
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for (i = 0; i < descs; i++) {
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ring[i] = ioat2_alloc_ring_ent(c);
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if (!ring[i]) {
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while (i--)
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ioat2_free_ring_ent(ring[i], c);
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kfree(ring);
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return -ENOMEM;
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}
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set_desc_id(ring[i], i);
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}
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/* link descs */
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for (i = 0; i < descs-1; i++) {
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struct ioat_ring_ent *next = ring[i+1];
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struct ioat_dma_descriptor *hw = ring[i]->hw;
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hw->next = next->txd.phys;
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}
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ring[i]->hw->next = ring[0]->txd.phys;
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spin_lock_bh(&ioat->ring_lock);
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ioat->ring = ring;
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@ -468,12 +505,120 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c)
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ioat->issued = 0;
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ioat->tail = 0;
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ioat->pending = 0;
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ioat->alloc_order = order;
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spin_unlock_bh(&ioat->ring_lock);
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tasklet_enable(&chan->cleanup_task);
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ioat2_start_null_desc(ioat);
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return descs;
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return 1 << ioat->alloc_order;
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}
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static bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
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{
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/* reshape differs from normal ring allocation in that we want
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* to allocate a new software ring while only
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* extending/truncating the hardware ring
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*/
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struct ioat_chan_common *chan = &ioat->base;
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struct dma_chan *c = &chan->common;
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const u16 curr_size = ioat2_ring_mask(ioat) + 1;
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const u16 active = ioat2_ring_active(ioat);
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const u16 new_size = 1 << order;
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struct ioat_ring_ent **ring;
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u16 i;
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if (order > ioat_get_max_alloc_order())
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return false;
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/* double check that we have at least 1 free descriptor */
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if (active == curr_size)
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return false;
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/* when shrinking, verify that we can hold the current active
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* set in the new ring
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*/
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if (active >= new_size)
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return false;
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/* allocate the array to hold the software ring */
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ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
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if (!ring)
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return false;
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/* allocate/trim descriptors as needed */
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if (new_size > curr_size) {
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/* copy current descriptors to the new ring */
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for (i = 0; i < curr_size; i++) {
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u16 curr_idx = (ioat->tail+i) & (curr_size-1);
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u16 new_idx = (ioat->tail+i) & (new_size-1);
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ring[new_idx] = ioat->ring[curr_idx];
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set_desc_id(ring[new_idx], new_idx);
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}
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/* add new descriptors to the ring */
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for (i = curr_size; i < new_size; i++) {
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u16 new_idx = (ioat->tail+i) & (new_size-1);
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ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT);
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if (!ring[new_idx]) {
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while (i--) {
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u16 new_idx = (ioat->tail+i) & (new_size-1);
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ioat2_free_ring_ent(ring[new_idx], c);
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}
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kfree(ring);
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return false;
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}
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set_desc_id(ring[new_idx], new_idx);
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}
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/* hw link new descriptors */
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for (i = curr_size-1; i < new_size; i++) {
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u16 new_idx = (ioat->tail+i) & (new_size-1);
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struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)];
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struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
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hw->next = next->txd.phys;
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}
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} else {
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struct ioat_dma_descriptor *hw;
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struct ioat_ring_ent *next;
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/* copy current descriptors to the new ring, dropping the
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* removed descriptors
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*/
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for (i = 0; i < new_size; i++) {
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u16 curr_idx = (ioat->tail+i) & (curr_size-1);
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u16 new_idx = (ioat->tail+i) & (new_size-1);
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ring[new_idx] = ioat->ring[curr_idx];
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set_desc_id(ring[new_idx], new_idx);
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}
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/* free deleted descriptors */
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for (i = new_size; i < curr_size; i++) {
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struct ioat_ring_ent *ent;
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ent = ioat2_get_ring_ent(ioat, ioat->tail+i);
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ioat2_free_ring_ent(ent, c);
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}
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/* fix up hardware ring */
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hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw;
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next = ring[(ioat->tail+new_size) & (new_size-1)];
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hw->next = next->txd.phys;
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}
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dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
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__func__, new_size);
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kfree(ioat->ring);
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ioat->ring = ring;
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ioat->alloc_order = order;
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return true;
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}
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/**
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@ -487,7 +632,15 @@ static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_d
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struct ioat_chan_common *chan = &ioat->base;
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spin_lock_bh(&ioat->ring_lock);
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if (unlikely(ioat2_ring_space(ioat) < num_descs)) {
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/* never allow the last descriptor to be consumed, we need at
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* least one free at all times to allow for on-the-fly ring
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* resizing.
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*/
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while (unlikely(ioat2_ring_space(ioat) <= num_descs)) {
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if (reshape_ring(ioat, ioat->alloc_order + 1) &&
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ioat2_ring_space(ioat) > num_descs)
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break;
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if (printk_ratelimit())
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dev_dbg(to_dev(chan),
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"%s: ring full! num_descs: %d (%x:%x:%x)\n",
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@ -37,6 +37,8 @@ extern int ioat_pending_level;
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#define IOAT_MAX_ORDER 16
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#define ioat_get_alloc_order() \
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(min(ioat_ring_alloc_order, IOAT_MAX_ORDER))
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#define ioat_get_max_alloc_order() \
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(min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER))
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/* struct ioat2_dma_chan - ioat v2 / v3 channel attributes
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* @base: common ioat channel parameters
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