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fbdev: sh_mipi_dsi: add HSxxCLK support

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SH MIPI manual explains the calculation method of HBP/HFP.
it is based on HSbyteCLK settings.
SH73a0 chip can use HS6divCLK/HS4divCLK for it.
This patch has compatibility to SH7372 mipi

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
This commit is contained in:
Kuninori Morimoto 2011-11-08 20:35:27 -08:00 • committed by Florian Tobias Schandinat
parent 5e47431aab
commit a2e6297153
4 changed files with 19 additions and 7 deletions
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5
arch/arm/mach-shmobile/board-ag5evm.c
View file

@ -357,8 +357,9 @@ static struct sh_mipi_dsi_info mipidsi0_info = {
.lane = 2, .lane = 2,
.vsynw_offset = 20, .vsynw_offset = 20,
.clksrc = 1, .clksrc = 1,
.flags = SH_MIPI_DSI_HSABM | .flags = SH_MIPI_DSI_HSABM |
SH_MIPI_DSI_SYNC_PULSES_MODE, SH_MIPI_DSI_SYNC_PULSES_MODE |
SH_MIPI_DSI_HSbyteCLK,
.set_dot_clock = sh_mipi_set_dot_clock, .set_dot_clock = sh_mipi_set_dot_clock,
}; };

3
arch/arm/mach-shmobile/board-ap4evb.c
View file

@ -606,7 +606,8 @@ static struct sh_mipi_dsi_info mipidsi0_info = {
.lcd_chan = &lcdc_info.ch[0], .lcd_chan = &lcdc_info.ch[0],
.lane = 2, .lane = 2,
.vsynw_offset = 17, .vsynw_offset = 17,
.flags = SH_MIPI_DSI_SYNC_PULSES_MODE, .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
SH_MIPI_DSI_HSbyteCLK,
.set_dot_clock = sh_mipi_set_dot_clock, .set_dot_clock = sh_mipi_set_dot_clock,
}; };

14
drivers/video/sh_mipi_dsi.c
View file

@ -153,7 +153,7 @@ static int __init sh_mipi_setup(struct sh_mipi *mipi,
void __iomem *base = mipi->base; void __iomem *base = mipi->base;
struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan; struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
u32 pctype, datatype, pixfmt, linelength, vmctr2; u32 pctype, datatype, pixfmt, linelength, vmctr2;
u32 tmp, top, bottom, delay; u32 tmp, top, bottom, delay, div;
bool yuv; bool yuv;
int bpp; int bpp;
@ -364,17 +364,23 @@ static int __init sh_mipi_setup(struct sh_mipi *mipi,
bottom = 0x00000001; bottom = 0x00000001;
delay = 0; delay = 0;
div = 1; /* HSbyteCLK is calculation base
* HS4divCLK = HSbyteCLK/2
* HS6divCLK is not supported for now */
if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
div = 2;
if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */ if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
top = ch->lcd_cfg[0].hsync_len + ch->lcd_cfg[0].left_margin; top = ch->lcd_cfg[0].hsync_len + ch->lcd_cfg[0].left_margin;
top = ((pdata->lane * top) - 10) << 16; top = ((pdata->lane * top / div) - 10) << 16;
} }
if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */ if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
bottom = ch->lcd_cfg[0].right_margin; bottom = ch->lcd_cfg[0].right_margin;
bottom = (pdata->lane * bottom) - 12; bottom = (pdata->lane * bottom / div) - 12;
} }
bpp = linelength / ch->lcd_cfg[0].xres; /* byte / pixel */ bpp = linelength / ch->lcd_cfg[0].xres; /* byte / pixel */
if (pdata->lane > bpp) { if ((pdata->lane / div) > bpp) {
tmp = ch->lcd_cfg[0].xres / bpp; /* output cycle */ tmp = ch->lcd_cfg[0].xres / bpp; /* output cycle */
tmp = ch->lcd_cfg[0].xres - tmp; /* (input - output) cycle */ tmp = ch->lcd_cfg[0].xres - tmp; /* (input - output) cycle */
delay = (pdata->lane * tmp); delay = (pdata->lane * tmp);

4
include/video/sh_mipi_dsi.h
View file

@ -35,6 +35,10 @@ struct sh_mobile_lcdc_chan_cfg;
#define SH_MIPI_DSI_HSEE (1 << 5) #define SH_MIPI_DSI_HSEE (1 << 5)
#define SH_MIPI_DSI_HSAE (1 << 6) #define SH_MIPI_DSI_HSAE (1 << 6)
#define SH_MIPI_DSI_HSbyteCLK (1 << 24)
#define SH_MIPI_DSI_HS6divCLK (1 << 25)
#define SH_MIPI_DSI_HS4divCLK (1 << 26)
#define SH_MIPI_DSI_SYNC_PULSES_MODE (SH_MIPI_DSI_VSEE | \ #define SH_MIPI_DSI_SYNC_PULSES_MODE (SH_MIPI_DSI_VSEE | \
SH_MIPI_DSI_HSEE | \ SH_MIPI_DSI_HSEE | \
SH_MIPI_DSI_HSAE) SH_MIPI_DSI_HSAE)