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mmc: sdhci-cadence: Fix writing PHY delay

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Add polling for ACK to be sure that data are written to PHY register.

Signed-off-by: Piotr Sroka <piotrs@cadence.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Piotr Sroka 2017-03-21 14:32:16 +00:00 committed by Ulf Hansson
parent bf3240bada
commit a0f8243229
1 changed files with 9 additions and 2 deletions
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11
drivers/mmc/host/sdhci-cadence.c
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@ -68,11 +68,12 @@ struct sdhci_cdns_priv {
bool enhanced_strobe; bool enhanced_strobe;
}; };
static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
u8 addr, u8 data) u8 addr, u8 data)
{ {
void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04; void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
u32 tmp; u32 tmp;
int ret;
tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
(addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
@ -81,8 +82,14 @@ static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
tmp |= SDHCI_CDNS_HRS04_WR; tmp |= SDHCI_CDNS_HRS04_WR;
writel(tmp, reg); writel(tmp, reg);
ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
if (ret)
return ret;
tmp &= ~SDHCI_CDNS_HRS04_WR; tmp &= ~SDHCI_CDNS_HRS04_WR;
writel(tmp, reg); writel(tmp, reg);
return 0;
} }
static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv) static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)