PCI: misc pci_reg additions
Fill in many missing definitions and add sizeof fields for many sections allowing for more extensive config parsing. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Alex Williamson
Bjorn Helgaas
parent
a696165140
commit
a0dee2ed0c
1 changed files with 101 additions and 12 deletions
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@ -26,6 +26,7 @@
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* Under PCI, each device has 256 bytes of configuration address space,
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* of which the first 64 bytes are standardized as follows:
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*/
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#define PCI_STD_HEADER_SIZEOF 64
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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@ -209,9 +210,12 @@
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#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
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#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
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#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
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#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
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#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
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#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
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#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
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#define PCI_CAP_ID_MAX PCI_CAP_ID_AF
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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@ -276,6 +280,7 @@
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#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
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#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
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#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
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#define PCI_CAP_VPD_SIZEOF 8
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/* Slot Identification */
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@ -297,8 +302,10 @@
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#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
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#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
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#define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */
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#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
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#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
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/* MSI-X registers */
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#define PCI_MSIX_FLAGS 2
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@ -308,6 +315,7 @@
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#define PCI_MSIX_TABLE 4
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#define PCI_MSIX_PBA 8
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#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
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#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
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/* MSI-X entry's format */
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#define PCI_MSIX_ENTRY_SIZE 16
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@ -338,6 +346,7 @@
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#define PCI_AF_CTRL_FLR 0x01
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#define PCI_AF_STATUS 5
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#define PCI_AF_STATUS_TP 0x01
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#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */
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/* PCI-X registers */
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@ -374,6 +383,10 @@
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#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
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#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
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#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
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#define PCI_X_ECC_CSR 8 /* ECC control and status */
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#define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */
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#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */
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#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */
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/* PCI Bridge Subsystem ID registers */
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@ -462,6 +475,7 @@
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#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
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#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
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#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */
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#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
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#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
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#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
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@ -521,6 +535,7 @@
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#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
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#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
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#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
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@ -529,23 +544,43 @@
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#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
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#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
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#define PCI_EXT_CAP_ID_ERR 1
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#define PCI_EXT_CAP_ID_VC 2
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#define PCI_EXT_CAP_ID_DSN 3
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#define PCI_EXT_CAP_ID_PWR 4
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#define PCI_EXT_CAP_ID_VNDR 11
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#define PCI_EXT_CAP_ID_ACS 13
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#define PCI_EXT_CAP_ID_ARI 14
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#define PCI_EXT_CAP_ID_ATS 15
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#define PCI_EXT_CAP_ID_SRIOV 16
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#define PCI_EXT_CAP_ID_PRI 19
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#define PCI_EXT_CAP_ID_LTR 24
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#define PCI_EXT_CAP_ID_PASID 27
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#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
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#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
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#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
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#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
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#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
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#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
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#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
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#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
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#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
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#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
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#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */
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#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
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#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
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#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
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#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
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#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
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#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
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#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
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#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
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#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */
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#define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */
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#define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */
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#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */
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#define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */
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#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */
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#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
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#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
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#define PCI_EXT_CAP_DSN_SIZEOF 12
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#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
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/* Advanced Error Reporting */
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#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
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#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
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#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
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#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */
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#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
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#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
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#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
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@ -555,6 +590,11 @@
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#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
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#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
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#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
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#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
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#define PCI_ERR_UNC_INTN 0x00400000 /* internal error */
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#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */
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#define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */
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#define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */
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#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
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/* Same bits as above */
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#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
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@ -565,6 +605,9 @@
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#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
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#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
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#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
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#define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
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#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */
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#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */
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#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
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/* Same bits as above */
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#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
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@ -596,12 +639,18 @@
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/* Virtual Channel */
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#define PCI_VC_PORT_REG1 4
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#define PCI_VC_REG1_EVCC 0x7 /* extended vc count */
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#define PCI_VC_PORT_REG2 8
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#define PCI_VC_REG2_32_PHASE 0x2
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#define PCI_VC_REG2_64_PHASE 0x4
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#define PCI_VC_REG2_128_PHASE 0x8
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#define PCI_VC_PORT_CTRL 12
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#define PCI_VC_PORT_STATUS 14
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#define PCI_VC_RES_CAP 16
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#define PCI_VC_RES_CTRL 20
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#define PCI_VC_RES_STATUS 26
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#define PCI_CAP_VC_BASE_SIZEOF 0x10
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#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C
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/* Power Budgeting */
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#define PCI_PWR_DSR 4 /* Data Select Register */
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@ -614,6 +663,7 @@
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#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
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#define PCI_PWR_CAP 12 /* Capability */
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#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
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#define PCI_EXT_CAP_PWR_SIZEOF 16
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/*
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* Hypertransport sub capability types
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@ -646,6 +696,8 @@
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#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
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#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */
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#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */
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#define HT_CAP_SIZEOF_LONG 28 /* slave & primary */
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#define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */
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/* Alternative Routing-ID Interpretation */
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#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
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@ -656,6 +708,7 @@
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#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
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#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
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#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
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#define PCI_EXT_CAP_ARI_SIZEOF 8
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/* Address Translation Service */
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#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
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@ -665,6 +718,7 @@
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#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
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#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
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#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
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#define PCI_EXT_CAP_ATS_SIZEOF 8
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/* Page Request Interface */
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#define PCI_PRI_CTRL 0x04 /* PRI control register */
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@ -676,6 +730,7 @@
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#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
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#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
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#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
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#define PCI_EXT_CAP_PRI_SIZEOF 16
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/* PASID capability */
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#define PCI_PASID_CAP 0x04 /* PASID feature register */
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@ -685,6 +740,7 @@
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#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
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#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
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#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */
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#define PCI_EXT_CAP_PASID_SIZEOF 8
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/* Single Root I/O Virtualization */
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#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
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@ -716,12 +772,14 @@
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#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
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#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
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#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
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#define PCI_EXT_CAP_SRIOV_SIZEOF 64
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#define PCI_LTR_MAX_SNOOP_LAT 0x4
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#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
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#define PCI_LTR_VALUE_MASK 0x000003ff
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#define PCI_LTR_SCALE_MASK 0x00001c00
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#define PCI_LTR_SCALE_SHIFT 10
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#define PCI_EXT_CAP_LTR_SIZEOF 8
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/* Access Control Service */
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#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
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@ -732,7 +790,38 @@
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#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
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#define PCI_ACS_EC 0x20 /* P2P Egress Control */
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#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
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#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
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#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
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#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
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#define PCI_VSEC_HDR 4 /* extended cap - vendor specific */
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#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */
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/* sata capability */
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#define PCI_SATA_REGS 4 /* SATA REGs specifier */
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#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
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#define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */
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#define PCI_SATA_SIZEOF_SHORT 8
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#define PCI_SATA_SIZEOF_LONG 16
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/* resizable BARs */
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#define PCI_REBAR_CTRL 8 /* control register */
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#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */
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#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */
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/* dynamic power allocation */
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#define PCI_DPA_CAP 4 /* capability register */
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#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
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#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */
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/* TPH Requester */
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#define PCI_TPH_CAP 4 /* capability register */
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#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */
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#define PCI_TPH_LOC_NONE 0x000 /* no location */
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#define PCI_TPH_LOC_CAP 0x200 /* in capability */
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#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
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#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */
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#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */
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#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */
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#endif /* LINUX_PCI_REGS_H */
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