x86, mrst: add cpu type detection
Medfield is the follow-up of Moorestown, it is treated under the same HW sub-architecture. However, we do need to know the CPU type in order for some of the driver to act accordingly. We also have different optimal clock configuration for each CPU type. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> LKML-Reference: <1274295685-6774-3-git-send-email-jacob.jun.pan@linux.intel.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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@ -11,8 +11,27 @@
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#ifndef _ASM_X86_MRST_H
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#define _ASM_X86_MRST_H
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extern int pci_mrst_init(void);
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extern int mrst_identify_cpu(void);
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int __init sfi_parse_mrtc(struct sfi_table_header *table);
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/*
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* Medfield is the follow-up of Moorestown, it combines two chip solution into
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* one. Other than that it also added always-on and constant tsc and lapic
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* timers. Medfield is the platform name, and the chip name is called Penwell
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* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
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* identified via MSRs.
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*/
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enum mrst_cpu_type {
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MRST_CPU_CHIP_LINCROFT = 1,
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MRST_CPU_CHIP_PENWELL,
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};
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enum mrst_timer_options {
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MRST_TIMER_DEFAULT,
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MRST_TIMER_APBT_ONLY,
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MRST_TIMER_LAPIC_APBT,
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};
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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@ -27,6 +27,8 @@
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static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
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static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
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static int mrst_cpu_chip;
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int sfi_mtimer_num;
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struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
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@ -216,6 +218,28 @@ static void __init mrst_setup_boot_clock(void)
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setup_boot_APIC_clock();
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};
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int mrst_identify_cpu(void)
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{
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return mrst_cpu_chip;
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}
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EXPORT_SYMBOL_GPL(mrst_identify_cpu);
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void __cpuinit mrst_arch_setup(void)
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{
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if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
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mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
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else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
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mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
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else {
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pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
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}
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pr_debug("Moorestown CPU %s identified\n",
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(mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
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"Lincroft" : "Penwell");
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}
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/*
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* Moorestown specific x86_init function overrides and early setup
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* calls.
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@ -230,6 +254,8 @@ void __init x86_mrst_early_setup(void)
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x86_init.irqs.pre_vector_init = x86_init_noop;
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x86_init.oem.arch_setup = mrst_arch_setup;
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x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;
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x86_platform.calibrate_tsc = mrst_calibrate_tsc;
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