ARM: kernel: add device tree init map function
When booting through a device tree, the kernel cpu logical id map can be initialized using device tree data passed by FW or through an embedded blob. This patch adds a function that parses device tree "cpu" nodes and retrieves the corresponding CPUs hardware identifiers (MPIDR). It sets the possible cpus and the cpu logical map values according to the number of CPUs defined in the device tree and respective properties. The device tree HW identifiers are considered valid if all CPU nodes contain a "reg" property, there are no duplicate "reg" entries and the DT defines a CPU node whose "reg" property matches the MPIDR[23:0] of the boot CPU. The primary CPU is assigned cpu logical number 0 to keep the current convention valid. Current bindings documentation is included in the patch: Documentation/devicetree/bindings/arm/cpus.txt Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org>
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Lorenzo Pieralisi
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77
Documentation/devicetree/bindings/arm/cpus.txt
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77
Documentation/devicetree/bindings/arm/cpus.txt
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@ -0,0 +1,77 @@
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* ARM CPUs binding description
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The device tree allows to describe the layout of CPUs in a system through
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the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
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defining properties for every cpu.
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Bindings for CPU nodes follow the ePAPR standard, available from:
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http://devicetree.org
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For the ARM architecture every CPU node must contain the following properties:
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- device_type: must be "cpu"
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- reg: property matching the CPU MPIDR[23:0] register bits
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reg[31:24] bits must be set to 0
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- compatible: should be one of:
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"arm,arm1020"
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"arm,arm1020e"
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"arm,arm1022"
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"arm,arm1026"
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"arm,arm720"
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"arm,arm740"
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"arm,arm7tdmi"
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"arm,arm920"
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"arm,arm922"
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"arm,arm925"
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"arm,arm926"
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"arm,arm940"
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"arm,arm946"
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"arm,arm9tdmi"
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"arm,cortex-a5"
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"arm,cortex-a7"
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"arm,cortex-a8"
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"arm,cortex-a9"
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"arm,cortex-a15"
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"arm,arm1136"
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"arm,arm1156"
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"arm,arm1176"
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"arm,arm11mpcore"
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"faraday,fa526"
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"intel,sa110"
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"intel,sa1100"
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"marvell,feroceon"
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"marvell,mohawk"
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"marvell,xsc3"
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"marvell,xscale"
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Example:
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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};
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};
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@ -15,6 +15,7 @@
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extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
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extern void arm_dt_memblock_reserve(void);
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extern void __init arm_dt_init_cpu_maps(void);
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#else /* CONFIG_OF */
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@ -24,6 +25,7 @@ static inline struct machine_desc *setup_machine_fdt(unsigned int dt_phys)
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}
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static inline void arm_dt_memblock_reserve(void) { }
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static inline void arm_dt_init_cpu_maps(void) { }
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#endif /* CONFIG_OF */
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#endif /* ASMARM_PROM_H */
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@ -19,8 +19,10 @@
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <asm/cputype.h>
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#include <asm/setup.h>
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#include <asm/page.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/arch.h>
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#include <asm/mach-types.h>
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@ -61,6 +63,104 @@ void __init arm_dt_memblock_reserve(void)
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}
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}
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/*
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* arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
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* and builds the cpu logical map array containing MPIDR values related to
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* logical cpus
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*
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* Updates the cpu possible mask with the number of parsed cpu nodes
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*/
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void __init arm_dt_init_cpu_maps(void)
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{
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/*
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* Temp logical map is initialized with UINT_MAX values that are
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* considered invalid logical map entries since the logical map must
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* contain a list of MPIDR[23:0] values where MPIDR[31:24] must
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* read as 0.
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*/
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struct device_node *cpu, *cpus;
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u32 i, j, cpuidx = 1;
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u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
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u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
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bool bootcpu_valid = false;
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cpus = of_find_node_by_path("/cpus");
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if (!cpus)
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return;
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for_each_child_of_node(cpus, cpu) {
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u32 hwid;
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pr_debug(" * %s...\n", cpu->full_name);
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/*
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* A device tree containing CPU nodes with missing "reg"
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* properties is considered invalid to build the
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* cpu_logical_map.
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*/
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if (of_property_read_u32(cpu, "reg", &hwid)) {
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pr_debug(" * %s missing reg property\n",
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cpu->full_name);
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return;
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}
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/*
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* 8 MSBs must be set to 0 in the DT since the reg property
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* defines the MPIDR[23:0].
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*/
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if (hwid & ~MPIDR_HWID_BITMASK)
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return;
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/*
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* Duplicate MPIDRs are a recipe for disaster.
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* Scan all initialized entries and check for
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* duplicates. If any is found just bail out.
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* temp values were initialized to UINT_MAX
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* to avoid matching valid MPIDR[23:0] values.
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*/
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for (j = 0; j < cpuidx; j++)
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if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
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"properties in the DT\n"))
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return;
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/*
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* Build a stashed array of MPIDR values. Numbering scheme
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* requires that if detected the boot CPU must be assigned
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* logical id 0. Other CPUs get sequential indexes starting
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* from 1. If a CPU node with a reg property matching the
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* boot CPU MPIDR is detected, this is recorded so that the
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* logical map built from DT is validated and can be used
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* to override the map created in smp_setup_processor_id().
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*/
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if (hwid == mpidr) {
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i = 0;
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bootcpu_valid = true;
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} else {
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i = cpuidx++;
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}
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tmp_map[i] = hwid;
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if (cpuidx > nr_cpu_ids)
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break;
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}
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if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
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"fall back to default cpu_logical_map\n"))
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return;
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/*
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* Since the boot CPU node contains proper data, and all nodes have
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* a reg property, the DT CPU list can be considered valid and the
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* logical map created in smp_setup_processor_id() can be overridden
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*/
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for (i = 0; i < cpuidx; i++) {
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set_cpu_possible(i, true);
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cpu_logical_map(i) = tmp_map[i];
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pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
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}
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}
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/**
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* setup_machine_fdt - Machine setup when an dtb was passed to the kernel
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* @dt_phys: physical address of dt blob
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