[PATCH] SPI: busnum == 0 needs to work
We need to be able to have a "SPI bus 0" matching chip numbering; but that number was wrongly used to flag dynamic allocation of a bus number. This patch resolves that issue; now negative numbers trigger dynamic alloc. It also updates the how-to-write-a-controller-driver overview to mention this stuff. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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3 changed files with 38 additions and 6 deletions
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@ -414,7 +414,33 @@ to get the driver-private data allocated for that device.
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The driver will initialize the fields of that spi_master, including the
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bus number (maybe the same as the platform device ID) and three methods
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used to interact with the SPI core and SPI protocol drivers. It will
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also initialize its own internal state.
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also initialize its own internal state. (See below about bus numbering
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and those methods.)
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After you initialize the spi_master, then use spi_register_master() to
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publish it to the rest of the system. At that time, device nodes for
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the controller and any predeclared spi devices will be made available,
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and the driver model core will take care of binding them to drivers.
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If you need to remove your SPI controller driver, spi_unregister_master()
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will reverse the effect of spi_register_master().
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BUS NUMBERING
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Bus numbering is important, since that's how Linux identifies a given
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SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On
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SOC systems, the bus numbers should match the numbers defined by the chip
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manufacturer. For example, hardware controller SPI2 would be bus number 2,
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and spi_board_info for devices connected to it would use that number.
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If you don't have such hardware-assigned bus number, and for some reason
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you can't just assign them, then provide a negative bus number. That will
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then be replaced by a dynamically assigned number. You'd then need to treat
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this as a non-static configuration (see above).
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SPI MASTER METHODS
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master->setup(struct spi_device *spi)
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This sets up the device clock rate, SPI mode, and word sizes.
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@ -431,6 +457,9 @@ also initialize its own internal state.
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state it dynamically associates with that device. If you do that,
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be sure to provide the cleanup() method to free that state.
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SPI MESSAGE QUEUE
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The bulk of the driver will be managing the I/O queue fed by transfer().
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That queue could be purely conceptual. For example, a driver used only
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@ -440,6 +469,9 @@ But the queue will probably be very real, using message->queue, PIO,
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often DMA (especially if the root filesystem is in SPI flash), and
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execution contexts like IRQ handlers, tasklets, or workqueues (such
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as keventd). Your driver can be as fancy, or as simple, as you need.
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Such a transfer() method would normally just add the message to a
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queue, and then start some asynchronous transfer engine (unless it's
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already running).
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THANKS TO
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@ -395,7 +395,7 @@ EXPORT_SYMBOL_GPL(spi_alloc_master);
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int __init_or_module
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spi_register_master(struct spi_master *master)
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{
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static atomic_t dyn_bus_id = ATOMIC_INIT(0);
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static atomic_t dyn_bus_id = ATOMIC_INIT((1<<16) - 1);
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struct device *dev = master->cdev.dev;
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int status = -ENODEV;
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int dynamic = 0;
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@ -404,7 +404,7 @@ spi_register_master(struct spi_master *master)
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return -ENODEV;
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/* convention: dynamically assigned bus IDs count down from the max */
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if (master->bus_num == 0) {
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if (master->bus_num < 0) {
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master->bus_num = atomic_dec_return(&dyn_bus_id);
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dynamic = 1;
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}
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@ -172,13 +172,13 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
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struct spi_master {
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struct class_device cdev;
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/* other than zero (== assign one dynamically), bus_num is fully
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/* other than negative (== assign one dynamically), bus_num is fully
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* board-specific. usually that simplifies to being SOC-specific.
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* example: one SOC has three SPI controllers, numbered 1..3,
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* example: one SOC has three SPI controllers, numbered 0..2,
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* and one board's schematics might show it using SPI-2. software
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* would normally use bus_num=2 for that controller.
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*/
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u16 bus_num;
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s16 bus_num;
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/* chipselects will be integral to many controllers; some others
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* might use board-specific GPIOs.
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