spi: dw-mid: split dma_setup() from dma_transfer()
The patch splits DMA preparatory code to dma_setup() callback. The change also converts transfer_one() to program DMA whenever the transfer is DMA mapped. The change is a follow up of the converion to use SPI core transfer_one_message(). Since the DMA mapped transfers can be interleaved with PIO ones the DMA related configuration should respect that. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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e31abce778
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9f14538ecd
3 changed files with 21 additions and 23 deletions
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@ -207,12 +207,10 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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return rxdesc;
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}
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static void dw_spi_dma_setup(struct dw_spi *dws)
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static int mid_spi_dma_setup(struct dw_spi *dws)
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{
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u16 dma_ctrl = 0;
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spi_enable_chip(dws, 0);
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dw_writew(dws, DW_SPI_DMARDLR, 0xf);
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dw_writew(dws, DW_SPI_DMATDLR, 0x10);
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@ -222,21 +220,17 @@ static void dw_spi_dma_setup(struct dw_spi *dws)
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dma_ctrl |= SPI_DMA_RDMAE;
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dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
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spi_enable_chip(dws, 1);
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return 0;
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}
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static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
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static int mid_spi_dma_transfer(struct dw_spi *dws)
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{
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struct dma_async_tx_descriptor *txdesc, *rxdesc;
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/* 1. setup DMA related registers */
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if (cs_change)
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dw_spi_dma_setup(dws);
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/* 2. Prepare the TX dma transfer */
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/* Prepare the TX dma transfer */
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txdesc = dw_spi_dma_prepare_tx(dws);
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/* 3. Prepare the RX dma transfer */
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/* Prepare the RX dma transfer */
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rxdesc = dw_spi_dma_prepare_rx(dws);
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/* rx must be started before tx due to spi instinct */
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@ -258,6 +252,7 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
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static struct dw_spi_dma_ops mid_dma_ops = {
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.dma_init = mid_spi_dma_init,
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.dma_exit = mid_spi_dma_exit,
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.dma_setup = mid_spi_dma_setup,
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.dma_transfer = mid_spi_dma_transfer,
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};
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#endif
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@ -316,11 +316,11 @@ static int dw_spi_transfer_one(struct spi_master *master,
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struct dw_spi *dws = spi_master_get_devdata(master);
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struct chip_data *chip = spi_get_ctldata(spi);
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u8 imask = 0;
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u8 cs_change = 0;
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u16 txlevel = 0;
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u16 clk_div = 0;
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u32 speed = 0;
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u32 cr0 = 0;
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int ret;
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dws->n_bytes = chip->n_bytes;
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dws->dma_width = chip->dma_width;
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@ -332,8 +332,6 @@ static int dw_spi_transfer_one(struct spi_master *master,
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dws->rx = transfer->rx_buf;
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dws->rx_end = dws->rx + transfer->len;
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dws->len = transfer->len;
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if (chip != dws->prev_chip)
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cs_change = 1;
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spi_enable_chip(dws, 0);
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@ -397,7 +395,13 @@ static int dw_spi_transfer_one(struct spi_master *master,
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* Interrupt mode
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* we only need set the TXEI IRQ, as TX/RX always happen syncronizely
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*/
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if (!dws->dma_mapped && !chip->poll_mode) {
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if (dws->dma_mapped) {
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ret = dws->dma_ops->dma_setup(dws);
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if (ret < 0) {
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spi_enable_chip(dws, 1);
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return ret;
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}
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} else if (!chip->poll_mode) {
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txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
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dw_writew(dws, DW_SPI_TXFLTR, txlevel);
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@ -411,11 +415,11 @@ static int dw_spi_transfer_one(struct spi_master *master,
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spi_enable_chip(dws, 1);
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if (cs_change)
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dws->prev_chip = chip;
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if (dws->dma_mapped)
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dws->dma_ops->dma_transfer(dws, cs_change);
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if (dws->dma_mapped) {
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ret = dws->dma_ops->dma_transfer(dws);
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if (ret < 0)
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return ret;
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}
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if (chip->poll_mode)
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return poll_transfer(dws);
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@ -546,7 +550,6 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
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dws->master = master;
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dws->type = SSI_MOTO_SPI;
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dws->prev_chip = NULL;
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dws->dma_inited = 0;
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dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
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snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
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@ -91,7 +91,8 @@ struct dw_spi;
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struct dw_spi_dma_ops {
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int (*dma_init)(struct dw_spi *dws);
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void (*dma_exit)(struct dw_spi *dws);
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int (*dma_transfer)(struct dw_spi *dws, int cs_change);
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int (*dma_setup)(struct dw_spi *dws);
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int (*dma_transfer)(struct dw_spi *dws);
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};
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struct dw_spi {
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@ -109,7 +110,6 @@ struct dw_spi {
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u16 num_cs; /* supported slave numbers */
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/* Current message transfer state info */
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struct chip_data *prev_chip;
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size_t len;
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void *tx;
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void *tx_end;
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