ARM: shmobile: r8a7790: add div4 clocks
DIV4 clocks control SD* core clocks. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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1 changed files with 32 additions and 0 deletions
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@ -51,6 +51,7 @@
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#define SMSTPCR7 0xe615014c
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#define MODEMR 0xE6160060
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#define SDCKCR 0xE6150074
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static struct clk_mapping cpg_mapping = {
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.phys = CPG_BASE,
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@ -131,6 +132,29 @@ static struct clk *main_clks[] = {
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&cp_clk,
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};
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/* SDHI (DIV4) clock */
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum {
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DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
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};
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
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[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
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[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
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};
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/* MSTP */
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enum { MSTP721, MSTP720,
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MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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@ -173,6 +197,11 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("qspi", &qspi_clk),
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CLKDEV_CON_ID("cp", &cp_clk),
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/* DIV4 */
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CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
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CLKDEV_CON_ID("sd0", &div4_clks[DIV4_SD0]),
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CLKDEV_CON_ID("sd1", &div4_clks[DIV4_SD1]),
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/* MSTP */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
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@ -232,6 +261,9 @@ void __init r8a7790_clock_init(void)
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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