ARM: shmobile: sh7372: sh7372_fsidivX_clk become non-global

Not only sh7372 but also many Renesas chip has FSI-DIV clock,
and we can share its sh_clk_ops.
To support common FSI-DIV clock, sh7372_fsidivX_clk
becomes non-global by this patch.
This is preparation for FSI DT support.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
This commit is contained in:
Kuninori Morimoto 2012-10-30 20:07:25 -07:00 committed by Simon Horman
parent 9d626eccb1
commit 9ee8008e99
4 changed files with 8 additions and 8 deletions

View file

@ -728,7 +728,7 @@ static int fsi_ak4642_set_rate(struct device *dev, int rate, int enable)
static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
{
struct clk *fsib_clk;
struct clk *fdiv_clk = &sh7372_fsidivb_clk;
struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
long fsib_rate = 0;
long fdiv_rate = 0;
int ackmd_bpfmd;

View file

@ -882,7 +882,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
static int fsi_b_set_rate(struct device *dev, int rate, int enable)
{
struct clk *fsib_clk;
struct clk *fdiv_clk = &sh7372_fsidivb_clk;
struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
long fsib_rate = 0;
long fdiv_rate = 0;
int ackmd_bpfmd;

View file

@ -481,7 +481,7 @@ static struct clk_mapping fsidiva_clk_mapping = {
.len = 8,
};
struct clk sh7372_fsidiva_clk = {
static struct clk fsidiva_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
.mapping = &fsidiva_clk_mapping,
@ -492,15 +492,15 @@ static struct clk_mapping fsidivb_clk_mapping = {
.len = 8,
};
struct clk sh7372_fsidivb_clk = {
static struct clk fsidivb_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
.mapping = &fsidivb_clk_mapping,
};
static struct clk *late_main_clks[] = {
&sh7372_fsidiva_clk,
&sh7372_fsidivb_clk,
&fsidiva_clk,
&fsidivb_clk,
};
enum { MSTP001, MSTP000,
@ -583,6 +583,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
CLKDEV_CON_ID("fsidiva", &fsidiva_clk),
CLKDEV_CON_ID("fsidivb", &fsidivb_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),

View file

@ -479,8 +479,6 @@ extern struct clk sh7372_dv_clki_div2_clk;
extern struct clk sh7372_pllc2_clk;
extern struct clk sh7372_fsiack_clk;
extern struct clk sh7372_fsibck_clk;
extern struct clk sh7372_fsidiva_clk;
extern struct clk sh7372_fsidivb_clk;
extern void sh7372_intcs_suspend(void);
extern void sh7372_intcs_resume(void);