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Blackfin: dpmc: optimize SDRAM programming slightly

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No need to reload these registers constantly since they're always
available (we're not making any function calls in between).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2011-06-27 15:46:40 -04:00
parent da31d6fb46
commit 9e770f7780
1 changed files with 10 additions and 9 deletions
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19
arch/blackfin/mach-common/dpmc_modes.S
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@ -196,21 +196,20 @@ ENTRY(_set_dram_srfs)
#else /* SDRAM */
P0.L = lo(EBIU_SDGCTL);
P0.H = hi(EBIU_SDGCTL);
P1.L = lo(EBIU_SDSTAT);
P1.H = hi(EBIU_SDSTAT);
R2 = [P0];
BITSET(R2, 24); /* SRFS enter self-refresh mode */
[P0] = R2;
SSYNC;
P0.L = lo(EBIU_SDSTAT);
P0.H = hi(EBIU_SDSTAT);
1:
R2 = w[P0];
R2 = w[P1];
SSYNC;
cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
if !cc jump 1b;
P0.L = lo(EBIU_SDGCTL);
P0.H = hi(EBIU_SDGCTL);
R2 = [P0];
BITCLR(R2, 0); /* SCTLE disable CLKOUT */
[P0] = R2;
@ -220,6 +219,7 @@ ENDPROC(_set_dram_srfs)
ENTRY(_unset_dram_srfs)
/* set the dram out of self refresh mode */
#if defined(EBIU_RSTCTL) /* DDR */
P0.H = hi(EBIU_RSTCTL);
P0.L = lo(EBIU_RSTCTL);
@ -227,20 +227,21 @@ ENTRY(_unset_dram_srfs)
BITCLR(R2, 3); /* clear SRREQ bit */
[P0] = R2;
#elif defined(EBIU_SDGCTL) /* SDRAM */
P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
/* release CLKOUT from self-refresh */
P0.L = lo(EBIU_SDGCTL);
P0.H = hi(EBIU_SDGCTL);
R2 = [P0];
BITSET(R2, 0); /* SCTLE enable CLKOUT */
[P0] = R2
SSYNC;
P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
P0.H = hi(EBIU_SDGCTL);
/* release SDRAM from self-refresh */
R2 = [P0];
BITCLR(R2, 24); /* clear SRFS bit */
[P0] = R2
#endif
SSYNC;
RTS;
ENDPROC(_unset_dram_srfs)