drm/radeon/kms: add support for gen2 pcie link speeds
Supported on rv6xx/r7xx/evergreen. Cards come up in gen1 mode. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
3313e3d433
commit
9e46a48df2
7 changed files with 348 additions and 0 deletions
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@ -39,6 +39,7 @@
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static void evergreen_gpu_init(struct radeon_device *rdev);
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void evergreen_fini(struct radeon_device *rdev);
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static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
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void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
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{
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@ -2767,6 +2768,9 @@ static int evergreen_startup(struct radeon_device *rdev)
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{
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int r;
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/* enable pcie gen2 link */
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evergreen_pcie_gen2_enable(rdev);
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if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
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r = r600_init_microcode(rdev);
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if (r) {
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@ -3049,3 +3053,52 @@ void evergreen_fini(struct radeon_device *rdev)
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rdev->bios = NULL;
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radeon_dummy_page_fini(rdev);
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}
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static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
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{
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u32 link_width_cntl, speed_cntl;
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if (rdev->flags & RADEON_IS_IGP)
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return;
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if (!(rdev->flags & RADEON_IS_PCIE))
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return;
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/* x2 cards have a special sequence */
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if (ASIC_IS_X2(rdev))
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return;
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
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(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
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link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
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link_width_cntl &= ~LC_UPCONFIGURE_DIS;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
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WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
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WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
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WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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speed_cntl |= LC_GEN2_EN_STRAP;
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WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
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} else {
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link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
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/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
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if (1)
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link_width_cntl |= LC_UPCONFIGURE_DIS;
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else
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link_width_cntl &= ~LC_UPCONFIGURE_DIS;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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}
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}
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@ -581,6 +581,44 @@
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# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
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# define DC_HPDx_EN (1 << 28)
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/* PCIE link stuff */
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#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
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#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
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# define LC_LINK_WIDTH_SHIFT 0
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# define LC_LINK_WIDTH_MASK 0x7
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# define LC_LINK_WIDTH_X0 0
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# define LC_LINK_WIDTH_X1 1
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# define LC_LINK_WIDTH_X2 2
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# define LC_LINK_WIDTH_X4 3
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# define LC_LINK_WIDTH_X8 4
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# define LC_LINK_WIDTH_X16 6
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# define LC_LINK_WIDTH_RD_SHIFT 4
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# define LC_LINK_WIDTH_RD_MASK 0x70
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# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
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# define LC_RECONFIG_NOW (1 << 8)
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# define LC_RENEGOTIATION_SUPPORT (1 << 9)
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# define LC_RENEGOTIATE_EN (1 << 10)
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# define LC_SHORT_RECONFIG_EN (1 << 11)
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# define LC_UPCONFIGURE_SUPPORT (1 << 12)
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# define LC_UPCONFIGURE_DIS (1 << 13)
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#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
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# define LC_GEN2_EN_STRAP (1 << 0)
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# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
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# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
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# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
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# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
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# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
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# define LC_CURRENT_DATA_RATE (1 << 11)
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# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
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# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
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# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
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# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
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#define MM_CFGREGS_CNTL 0x544c
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# define MM_WR_TO_CFG_EN (1 << 3)
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#define LINK_CNTL2 0x88 /* F0 */
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# define TARGET_LINK_SPEED_MASK (0xf << 0)
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# define SELECTABLE_DEEMPHASIS (1 << 6)
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/*
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* PM4
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*/
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@ -94,6 +94,7 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
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void r600_gpu_init(struct radeon_device *rdev);
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void r600_fini(struct radeon_device *rdev);
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void r600_irq_disable(struct radeon_device *rdev);
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static void r600_pcie_gen2_enable(struct radeon_device *rdev);
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/* get temperature in millidegrees */
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u32 rv6xx_get_temp(struct radeon_device *rdev)
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@ -2379,6 +2380,9 @@ int r600_startup(struct radeon_device *rdev)
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{
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int r;
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/* enable pcie gen2 link */
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r600_pcie_gen2_enable(rdev);
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if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
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r = r600_init_microcode(rdev);
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if (r) {
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@ -3649,3 +3653,101 @@ int r600_get_pcie_lanes(struct radeon_device *rdev)
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}
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}
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static void r600_pcie_gen2_enable(struct radeon_device *rdev)
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{
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u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
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u16 link_cntl2;
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if (rdev->flags & RADEON_IS_IGP)
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return;
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if (!(rdev->flags & RADEON_IS_PCIE))
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return;
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/* x2 cards have a special sequence */
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if (ASIC_IS_X2(rdev))
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return;
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/* only RV6xx+ chips are supported */
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if (rdev->family <= CHIP_R600)
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return;
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/* 55 nm r6xx asics */
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if ((rdev->family == CHIP_RV670) ||
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(rdev->family == CHIP_RV620) ||
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(rdev->family == CHIP_RV635)) {
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/* advertise upconfig capability */
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link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
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link_width_cntl &= ~LC_UPCONFIGURE_DIS;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
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if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
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lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
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link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
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LC_RECONFIG_ARC_MISSING_ESCAPE);
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link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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} else {
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link_width_cntl |= LC_UPCONFIGURE_DIS;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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}
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}
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
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(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
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/* 55 nm r6xx asics */
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if ((rdev->family == CHIP_RV670) ||
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(rdev->family == CHIP_RV620) ||
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(rdev->family == CHIP_RV635)) {
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WREG32(MM_CFGREGS_CNTL, 0x8);
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link_cntl2 = RREG32(0x4088);
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WREG32(MM_CFGREGS_CNTL, 0);
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/* not supported yet */
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if (link_cntl2 & SELECTABLE_DEEMPHASIS)
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return;
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}
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speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
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speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
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speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
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speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
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speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
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WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
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tmp = RREG32(0x541c);
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WREG32(0x541c, tmp | 0x8);
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WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
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link_cntl2 = RREG16(0x4088);
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link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
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link_cntl2 |= 0x2;
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WREG16(0x4088, link_cntl2);
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WREG32(MM_CFGREGS_CNTL, 0);
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if ((rdev->family == CHIP_RV670) ||
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(rdev->family == CHIP_RV620) ||
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(rdev->family == CHIP_RV635)) {
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training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
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training_cntl &= ~LC_POINT_7_PLUS_EN;
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WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
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} else {
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
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WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
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}
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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speed_cntl |= LC_GEN2_EN_STRAP;
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WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
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} else {
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link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
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/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
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if (1)
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link_width_cntl |= LC_UPCONFIGURE_DIS;
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else
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link_width_cntl &= ~LC_UPCONFIGURE_DIS;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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}
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}
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@ -737,6 +737,45 @@
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# define DxGRPH_PFLIP_INT_MASK (1 << 0)
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# define DxGRPH_PFLIP_INT_TYPE (1 << 8)
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/* PCIE link stuff */
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#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
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# define LC_POINT_7_PLUS_EN (1 << 6)
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#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
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# define LC_LINK_WIDTH_SHIFT 0
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# define LC_LINK_WIDTH_MASK 0x7
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# define LC_LINK_WIDTH_X0 0
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# define LC_LINK_WIDTH_X1 1
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# define LC_LINK_WIDTH_X2 2
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# define LC_LINK_WIDTH_X4 3
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# define LC_LINK_WIDTH_X8 4
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# define LC_LINK_WIDTH_X16 6
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# define LC_LINK_WIDTH_RD_SHIFT 4
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# define LC_LINK_WIDTH_RD_MASK 0x70
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# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
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# define LC_RECONFIG_NOW (1 << 8)
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# define LC_RENEGOTIATION_SUPPORT (1 << 9)
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# define LC_RENEGOTIATE_EN (1 << 10)
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# define LC_SHORT_RECONFIG_EN (1 << 11)
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# define LC_UPCONFIGURE_SUPPORT (1 << 12)
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# define LC_UPCONFIGURE_DIS (1 << 13)
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#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
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# define LC_GEN2_EN_STRAP (1 << 0)
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# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
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# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
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# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
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# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
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# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
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# define LC_CURRENT_DATA_RATE (1 << 11)
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# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
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# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
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# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
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# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
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#define MM_CFGREGS_CNTL 0x544c
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# define MM_WR_TO_CFG_EN (1 << 3)
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#define LINK_CNTL2 0x88 /* F0 */
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# define TARGET_LINK_SPEED_MASK (0xf << 0)
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# define SELECTABLE_DEEMPHASIS (1 << 6)
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/*
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* PM4
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*/
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@ -1244,6 +1244,8 @@ static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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*/
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#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
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#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
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#define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
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#define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
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#define RREG32(reg) r100_mm_rreg(rdev, (reg))
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#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
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#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
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@ -41,6 +41,7 @@
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static void rv770_gpu_init(struct radeon_device *rdev);
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void rv770_fini(struct radeon_device *rdev);
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static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
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u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
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{
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@ -1124,6 +1125,9 @@ static int rv770_startup(struct radeon_device *rdev)
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{
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int r;
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/* enable pcie gen2 link */
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rv770_pcie_gen2_enable(rdev);
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if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
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r = r600_init_microcode(rdev);
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if (r) {
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@ -1362,3 +1366,75 @@ void rv770_fini(struct radeon_device *rdev)
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rdev->bios = NULL;
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radeon_dummy_page_fini(rdev);
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}
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static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
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{
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u32 link_width_cntl, lanes, speed_cntl, tmp;
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u16 link_cntl2;
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if (rdev->flags & RADEON_IS_IGP)
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return;
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if (!(rdev->flags & RADEON_IS_PCIE))
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return;
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/* x2 cards have a special sequence */
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if (ASIC_IS_X2(rdev))
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return;
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/* advertise upconfig capability */
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link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
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link_width_cntl &= ~LC_UPCONFIGURE_DIS;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
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if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
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lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
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link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
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LC_RECONFIG_ARC_MISSING_ESCAPE);
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link_width_cntl |= lanes | LC_RECONFIG_NOW |
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LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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} else {
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link_width_cntl |= LC_UPCONFIGURE_DIS;
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WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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}
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
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(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
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tmp = RREG32(0x541c);
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WREG32(0x541c, tmp | 0x8);
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WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
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link_cntl2 = RREG16(0x4088);
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link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
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link_cntl2 |= 0x2;
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WREG16(0x4088, link_cntl2);
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WREG32(MM_CFGREGS_CNTL, 0);
|
||||
|
||||
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
|
||||
speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
|
||||
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
|
||||
|
||||
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
|
||||
speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
|
||||
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
|
||||
|
||||
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
|
||||
speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
|
||||
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
|
||||
|
||||
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
|
||||
speed_cntl |= LC_GEN2_EN_STRAP;
|
||||
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
|
||||
|
||||
} else {
|
||||
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
|
||||
/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
|
||||
if (1)
|
||||
link_width_cntl |= LC_UPCONFIGURE_DIS;
|
||||
else
|
||||
link_width_cntl &= ~LC_UPCONFIGURE_DIS;
|
||||
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -360,4 +360,42 @@
|
|||
#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
|
||||
#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
|
||||
|
||||
/* PCIE link stuff */
|
||||
#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
|
||||
#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
|
||||
# define LC_LINK_WIDTH_SHIFT 0
|
||||
# define LC_LINK_WIDTH_MASK 0x7
|
||||
# define LC_LINK_WIDTH_X0 0
|
||||
# define LC_LINK_WIDTH_X1 1
|
||||
# define LC_LINK_WIDTH_X2 2
|
||||
# define LC_LINK_WIDTH_X4 3
|
||||
# define LC_LINK_WIDTH_X8 4
|
||||
# define LC_LINK_WIDTH_X16 6
|
||||
# define LC_LINK_WIDTH_RD_SHIFT 4
|
||||
# define LC_LINK_WIDTH_RD_MASK 0x70
|
||||
# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
|
||||
# define LC_RECONFIG_NOW (1 << 8)
|
||||
# define LC_RENEGOTIATION_SUPPORT (1 << 9)
|
||||
# define LC_RENEGOTIATE_EN (1 << 10)
|
||||
# define LC_SHORT_RECONFIG_EN (1 << 11)
|
||||
# define LC_UPCONFIGURE_SUPPORT (1 << 12)
|
||||
# define LC_UPCONFIGURE_DIS (1 << 13)
|
||||
#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
|
||||
# define LC_GEN2_EN_STRAP (1 << 0)
|
||||
# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
|
||||
# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
|
||||
# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
|
||||
# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
|
||||
# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
|
||||
# define LC_CURRENT_DATA_RATE (1 << 11)
|
||||
# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
|
||||
# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
|
||||
# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
|
||||
# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
|
||||
#define MM_CFGREGS_CNTL 0x544c
|
||||
# define MM_WR_TO_CFG_EN (1 << 3)
|
||||
#define LINK_CNTL2 0x88 /* F0 */
|
||||
# define TARGET_LINK_SPEED_MASK (0xf << 0)
|
||||
# define SELECTABLE_DEEMPHASIS (1 << 6)
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in a new issue