clk: basic clock hardware types
Many platforms support simple gateable clocks, fixed-rate clocks, adjustable divider clocks and multi-parent multiplexer clocks. This patch introduces basic clock types for the above-mentioned hardware which share some common characteristics. Based on original work by Jeremy Kerr and contribution by Jamie Iles. Dividers and multiplexor clocks originally contributed by Richard Zhao & Sascha Hauer. Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Mike Turquette <mturquette@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Jeremy Kerr <jeremy.kerr@canonical.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Arnd Bergman <arnd.bergmann@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Jamie Iles <jamie@jamieiles.com> Cc: Richard Zhao <richard.zhao@linaro.org> Cc: Saravana Kannan <skannan@codeaurora.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Deepak Saxena <dsaxena@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Mike Turquette
Arnd Bergmann
parent
b2476490ef
commit
9d9f78ed9a
7 changed files with 801 additions and 1 deletions
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@ -1,3 +1,4 @@
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obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
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obj-$(CONFIG_COMMON_CLK) += clk.o
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
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clk-mux.o clk-divider.o
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200
drivers/clk/clk-divider.c
Normal file
200
drivers/clk/clk-divider.c
Normal file
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@ -0,0 +1,200 @@
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/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable divider clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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/*
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* DOC: basic adjustable divider clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable. clk->rate = parent->rate / divisor
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#define div_mask(d) ((1 << (d->width)) - 1)
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static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div;
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div = readl(divider->reg) >> divider->shift;
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div &= div_mask(divider);
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
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div++;
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return parent_rate / div;
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}
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EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
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/*
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* The reverse of DIV_ROUND_UP: The maximum number which
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* divided by m is r
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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if (!rate)
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rate = 1;
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maxdiv = (1 << divider->width);
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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maxdiv--;
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if (!best_parent_rate) {
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parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
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bestdiv = DIV_ROUND_UP(parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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}
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * i below
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*/
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 1; i <= maxdiv; i++) {
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parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
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MULT_ROUND_UP(rate, i));
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now = parent_rate / i;
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if (now <= rate && now > best) {
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bestdiv = i;
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best = now;
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*best_parent_rate = parent_rate;
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}
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}
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if (!bestdiv) {
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bestdiv = (1 << divider->width);
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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bestdiv--;
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*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
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}
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return bestdiv;
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}
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static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int div;
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div = clk_divider_bestdiv(hw, rate, prate);
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if (prate)
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return *prate / div;
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else {
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unsigned long r;
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r = __clk_get_rate(__clk_get_parent(hw->clk));
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return r / div;
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}
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}
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EXPORT_SYMBOL_GPL(clk_divider_round_rate);
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static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div;
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unsigned long flags = 0;
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u32 val;
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div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
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div--;
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if (div > div_mask(divider))
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div = div_mask(divider);
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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val = readl(divider->reg);
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val &= ~(div_mask(divider) << divider->shift);
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val |= div << divider->shift;
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writel(val, divider->reg);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(clk_divider_set_rate);
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struct clk_ops clk_divider_ops = {
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.recalc_rate = clk_divider_recalc_rate,
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.round_rate = clk_divider_round_rate,
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.set_rate = clk_divider_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_divider_ops);
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struct clk *clk_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_divider *div;
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struct clk *clk;
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div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
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if (!div) {
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pr_err("%s: could not allocate divider clk\n", __func__);
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return NULL;
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}
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/* struct clk_divider assignments */
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div->reg = reg;
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->lock = lock;
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if (parent_name) {
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div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
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if (!div->parent[0])
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goto out;
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}
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clk = clk_register(dev, name,
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&clk_divider_ops, &div->hw,
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div->parent,
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(parent_name ? 1 : 0),
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flags);
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if (clk)
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return clk;
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out:
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kfree(div->parent[0]);
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kfree(div);
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return NULL;
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}
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82
drivers/clk/clk-fixed-rate.c
Normal file
82
drivers/clk/clk-fixed-rate.c
Normal file
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@ -0,0 +1,82 @@
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/*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Fixed rate clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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/*
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* DOC: basic fixed-rate clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parents are prepared
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* enable - clk_enable only ensures parents are enabled
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* rate - rate is always a fixed value. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
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static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return to_clk_fixed_rate(hw)->fixed_rate;
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}
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EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
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struct clk_ops clk_fixed_rate_ops = {
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.recalc_rate = clk_fixed_rate_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
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struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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unsigned long fixed_rate)
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{
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struct clk_fixed_rate *fixed;
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char **parent_names = NULL;
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u8 len;
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fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
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if (!fixed) {
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pr_err("%s: could not allocate fixed clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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/* struct clk_fixed_rate assignments */
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fixed->fixed_rate = fixed_rate;
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if (parent_name) {
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parent_names = kmalloc(sizeof(char *), GFP_KERNEL);
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if (! parent_names)
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goto out;
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len = sizeof(char) * strlen(parent_name);
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parent_names[0] = kmalloc(len, GFP_KERNEL);
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if (!parent_names[0])
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goto out;
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strncpy(parent_names[0], parent_name, len);
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}
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out:
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return clk_register(dev, name,
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&clk_fixed_rate_ops, &fixed->hw,
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parent_names,
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(parent_name ? 1 : 0),
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flags);
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}
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150
drivers/clk/clk-gate.c
Normal file
150
drivers/clk/clk-gate.c
Normal file
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/*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Gated clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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/**
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* DOC: basic gatable clock which can gate and ungate it's ouput
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable and clk_disable are functional & control gating
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* rate - inherits rate from parent. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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static void clk_gate_set_bit(struct clk_gate *gate)
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{
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u32 reg;
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unsigned long flags = 0;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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reg = readl(gate->reg);
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reg |= BIT(gate->bit_idx);
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writel(reg, gate->reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static void clk_gate_clear_bit(struct clk_gate *gate)
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{
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u32 reg;
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unsigned long flags = 0;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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reg = readl(gate->reg);
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reg &= ~BIT(gate->bit_idx);
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writel(reg, gate->reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static int clk_gate_enable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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if (gate->flags & CLK_GATE_SET_TO_DISABLE)
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clk_gate_clear_bit(gate);
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else
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clk_gate_set_bit(gate);
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return 0;
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}
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EXPORT_SYMBOL_GPL(clk_gate_enable);
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static void clk_gate_disable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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if (gate->flags & CLK_GATE_SET_TO_DISABLE)
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clk_gate_set_bit(gate);
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else
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clk_gate_clear_bit(gate);
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}
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EXPORT_SYMBOL_GPL(clk_gate_disable);
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static int clk_gate_is_enabled(struct clk_hw *hw)
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{
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u32 reg;
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struct clk_gate *gate = to_clk_gate(hw);
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reg = readl(gate->reg);
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/* if a set bit disables this clk, flip it before masking */
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if (gate->flags & CLK_GATE_SET_TO_DISABLE)
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reg ^= BIT(gate->bit_idx);
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reg &= BIT(gate->bit_idx);
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return reg ? 1 : 0;
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}
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EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
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struct clk_ops clk_gate_ops = {
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.enable = clk_gate_enable,
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.disable = clk_gate_disable,
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.is_enabled = clk_gate_is_enabled,
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};
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EXPORT_SYMBOL_GPL(clk_gate_ops);
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struct clk *clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock)
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{
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struct clk_gate *gate;
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struct clk *clk;
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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if (!gate) {
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pr_err("%s: could not allocate gated clk\n", __func__);
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return NULL;
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}
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/* struct clk_gate assignments */
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gate->reg = reg;
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gate->bit_idx = bit_idx;
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gate->flags = clk_gate_flags;
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gate->lock = lock;
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if (parent_name) {
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gate->parent[0] = kstrdup(parent_name, GFP_KERNEL);
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if (!gate->parent[0])
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goto out;
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}
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clk = clk_register(dev, name,
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&clk_gate_ops, &gate->hw,
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gate->parent,
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(parent_name ? 1 : 0),
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flags);
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if (clk)
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return clk;
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out:
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kfree(gate->parent[0]);
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kfree(gate);
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return NULL;
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}
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116
drivers/clk/clk-mux.c
Normal file
116
drivers/clk/clk-mux.c
Normal file
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@ -0,0 +1,116 @@
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/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
|
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
|
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
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* Simple multiplexer clock implementation
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
/*
|
||||
* DOC: basic adjustable multiplexer clock that cannot gate
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_prepare only ensures that parents are prepared
|
||||
* enable - clk_enable only ensures that parents are enabled
|
||||
* rate - rate is only affected by parent switching. No clk_set_rate support
|
||||
* parent - parent is adjustable through clk_set_parent
|
||||
*/
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
static u8 clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* FIXME need a mux-specific flag to determine if val is bitwise or numeric
|
||||
* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
|
||||
* to 0x7 (index starts at one)
|
||||
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
|
||||
* val = 0x4 really means "bit 2, index starts at bit 0"
|
||||
*/
|
||||
val = readl(mux->reg) >> mux->shift;
|
||||
val &= (1 << mux->width) - 1;
|
||||
|
||||
if (val && (mux->flags & CLK_MUX_INDEX_BIT))
|
||||
val = ffs(val) - 1;
|
||||
|
||||
if (val && (mux->flags & CLK_MUX_INDEX_ONE))
|
||||
val--;
|
||||
|
||||
if (val >= __clk_get_num_parents(hw->clk))
|
||||
return -EINVAL;
|
||||
|
||||
return val;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_mux_get_parent);
|
||||
|
||||
static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
u32 val;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (mux->flags & CLK_MUX_INDEX_BIT)
|
||||
index = (1 << ffs(index));
|
||||
|
||||
if (mux->flags & CLK_MUX_INDEX_ONE)
|
||||
index++;
|
||||
|
||||
if (mux->lock)
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
|
||||
val = readl(mux->reg);
|
||||
val &= ~(((1 << mux->width) - 1) << mux->shift);
|
||||
val |= index << mux->shift;
|
||||
writel(val, mux->reg);
|
||||
|
||||
if (mux->lock)
|
||||
spin_unlock_irqrestore(mux->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_mux_set_parent);
|
||||
|
||||
struct clk_ops clk_mux_ops = {
|
||||
.get_parent = clk_mux_get_parent,
|
||||
.set_parent = clk_mux_set_parent,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_mux_ops);
|
||||
|
||||
struct clk *clk_register_mux(struct device *dev, const char *name,
|
||||
char **parent_names, u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mux_flags, spinlock_t *lock)
|
||||
{
|
||||
struct clk_mux *mux;
|
||||
|
||||
mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL);
|
||||
|
||||
if (!mux) {
|
||||
pr_err("%s: could not allocate mux clk\n", __func__);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
/* struct clk_mux assignments */
|
||||
mux->reg = reg;
|
||||
mux->shift = shift;
|
||||
mux->width = width;
|
||||
mux->flags = clk_mux_flags;
|
||||
mux->lock = lock;
|
||||
|
||||
return clk_register(dev, name, &clk_mux_ops, &mux->hw,
|
||||
parent_names, num_parents, flags);
|
||||
}
|
||||
|
|
@ -46,6 +46,130 @@ struct clk {
|
|||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* DOC: Basic clock implementations common to many platforms
|
||||
*
|
||||
* Each basic clock hardware type is comprised of a structure describing the
|
||||
* clock hardware, implementations of the relevant callbacks in struct clk_ops,
|
||||
* unique flags for that hardware type, a registration function and an
|
||||
* alternative macro for static initialization
|
||||
*/
|
||||
|
||||
extern struct clk_ops clk_fixed_rate_ops;
|
||||
|
||||
#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
|
||||
_fixed_rate_flags) \
|
||||
static struct clk _name; \
|
||||
static char *_name##_parent_names[] = {}; \
|
||||
static struct clk_fixed_rate _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.fixed_rate = _rate, \
|
||||
.flags = _fixed_rate_flags, \
|
||||
}; \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_fixed_rate_ops, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _name##_parent_names, \
|
||||
.num_parents = \
|
||||
ARRAY_SIZE(_name##_parent_names), \
|
||||
.flags = _flags, \
|
||||
};
|
||||
|
||||
extern struct clk_ops clk_gate_ops;
|
||||
|
||||
#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
|
||||
_flags, _reg, _bit_idx, \
|
||||
_gate_flags, _lock) \
|
||||
static struct clk _name; \
|
||||
static char *_name##_parent_names[] = { \
|
||||
_parent_name, \
|
||||
}; \
|
||||
static struct clk *_name##_parents[] = { \
|
||||
_parent_ptr, \
|
||||
}; \
|
||||
static struct clk_gate _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.reg = _reg, \
|
||||
.bit_idx = _bit_idx, \
|
||||
.flags = _gate_flags, \
|
||||
.lock = _lock, \
|
||||
}; \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_gate_ops, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _name##_parent_names, \
|
||||
.num_parents = \
|
||||
ARRAY_SIZE(_name##_parent_names), \
|
||||
.parents = _name##_parents, \
|
||||
.flags = _flags, \
|
||||
};
|
||||
|
||||
extern struct clk_ops clk_divider_ops;
|
||||
|
||||
#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
|
||||
_flags, _reg, _shift, _width, \
|
||||
_divider_flags, _lock) \
|
||||
static struct clk _name; \
|
||||
static char *_name##_parent_names[] = { \
|
||||
_parent_name, \
|
||||
}; \
|
||||
static struct clk *_name##_parents[] = { \
|
||||
_parent_ptr, \
|
||||
}; \
|
||||
static struct clk_divider _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.flags = _divider_flags, \
|
||||
.lock = _lock, \
|
||||
}; \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_divider_ops, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _name##_parent_names, \
|
||||
.num_parents = \
|
||||
ARRAY_SIZE(_name##_parent_names), \
|
||||
.parents = _name##_parents, \
|
||||
.flags = _flags, \
|
||||
};
|
||||
|
||||
extern struct clk_ops clk_mux_ops;
|
||||
|
||||
#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
|
||||
_reg, _shift, _width, \
|
||||
_mux_flags, _lock) \
|
||||
static struct clk _name; \
|
||||
static struct clk_mux _name##_hw = { \
|
||||
.hw = { \
|
||||
.clk = &_name, \
|
||||
}, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.flags = _mux_flags, \
|
||||
.lock = _lock, \
|
||||
}; \
|
||||
static struct clk _name = { \
|
||||
.name = #_name, \
|
||||
.ops = &clk_mux_ops, \
|
||||
.hw = &_name##_hw.hw, \
|
||||
.parent_names = _parent_names, \
|
||||
.num_parents = \
|
||||
ARRAY_SIZE(_parent_names), \
|
||||
.parents = _parents, \
|
||||
.flags = _flags, \
|
||||
};
|
||||
|
||||
/**
|
||||
* __clk_init - initialize the data structures in a struct clk
|
||||
* @dev: device initializing this clk, placeholder for now
|
||||
|
|
|
|||
|
|
@ -129,6 +129,133 @@ struct clk_ops {
|
|||
void (*init)(struct clk_hw *hw);
|
||||
};
|
||||
|
||||
/*
|
||||
* DOC: Basic clock implementations common to many platforms
|
||||
*
|
||||
* Each basic clock hardware type is comprised of a structure describing the
|
||||
* clock hardware, implementations of the relevant callbacks in struct clk_ops,
|
||||
* unique flags for that hardware type, a registration function and an
|
||||
* alternative macro for static initialization
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct clk_fixed_rate - fixed-rate clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @fixed_rate: constant frequency of clock
|
||||
*/
|
||||
struct clk_fixed_rate {
|
||||
struct clk_hw hw;
|
||||
unsigned long fixed_rate;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
unsigned long fixed_rate);
|
||||
|
||||
/**
|
||||
* struct clk_gate - gating clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @reg: register controlling gate
|
||||
* @bit_idx: single bit controlling gate
|
||||
* @flags: hardware-specific flags
|
||||
* @lock: register lock
|
||||
*
|
||||
* Clock which can gate its output. Implements .enable & .disable
|
||||
*
|
||||
* Flags:
|
||||
* CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to
|
||||
* enable the clock. Setting this flag does the opposite: setting the bit
|
||||
* disable the clock and clearing it enables the clock
|
||||
*/
|
||||
struct clk_gate {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u8 bit_idx;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
char *parent[1];
|
||||
};
|
||||
|
||||
#define CLK_GATE_SET_TO_DISABLE BIT(0)
|
||||
|
||||
struct clk *clk_register_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct clk_divider - adjustable divider clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @reg: register containing the divider
|
||||
* @shift: shift to the divider bit field
|
||||
* @width: width of the divider bit field
|
||||
* @lock: register lock
|
||||
*
|
||||
* Clock with an adjustable divider affecting its output frequency. Implements
|
||||
* .recalc_rate, .set_rate and .round_rate
|
||||
*
|
||||
* Flags:
|
||||
* CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
|
||||
* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
|
||||
* the raw value read from the register, with the value of zero considered
|
||||
* invalid
|
||||
* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
|
||||
* the hardware register
|
||||
*/
|
||||
struct clk_divider {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
char *parent[1];
|
||||
};
|
||||
|
||||
#define CLK_DIVIDER_ONE_BASED BIT(0)
|
||||
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
|
||||
|
||||
struct clk *clk_register_divider(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct clk_mux - multiplexer clock
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @reg: register controlling multiplexer
|
||||
* @shift: shift to multiplexer bit field
|
||||
* @width: width of mutliplexer bit field
|
||||
* @num_clks: number of parent clocks
|
||||
* @lock: register lock
|
||||
*
|
||||
* Clock with multiple selectable parents. Implements .get_parent, .set_parent
|
||||
* and .recalc_rate
|
||||
*
|
||||
* Flags:
|
||||
* CLK_MUX_INDEX_ONE - register index starts at 1, not 0
|
||||
* CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two)
|
||||
*/
|
||||
struct clk_mux {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define CLK_MUX_INDEX_ONE BIT(0)
|
||||
#define CLK_MUX_INDEX_BIT BIT(1)
|
||||
|
||||
struct clk *clk_register_mux(struct device *dev, const char *name,
|
||||
char **parent_names, u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mux_flags, spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* clk_register - allocate a new clock, register it and return an opaque cookie
|
||||
|
|
|
|||
Loading…
Reference in a new issue