Merge master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6: ide: ide_scan_pcibus(): check __pci_register_driver return value ide: pdc202xx_new PLL input clock fix it821x: fix incorrect SWDMA mask amd74xx: resume fix hpt366: use correct enablebits for HPT36x hpt366: blacklist MAXTOR STM3320620A for UltraDMA/66 ide: Fix a theoretical Ooops case ide: never called printk statement in ide-taskfile.c::wait_drive_not_busy
This commit is contained in:
Linus Torvalds
commit
9d7542f891
7 changed files with 45 additions and 23 deletions
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@ -574,11 +574,11 @@ static inline u8 probe_for_drive (ide_drive_t *drive)
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/* look for ATAPI device */
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(void) do_probe(drive, WIN_PIDENTIFY);
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}
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if (strstr(drive->id->model, "E X A B Y T E N E S T"))
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enable_nest(drive);
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if (!drive->present)
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/* drive not found */
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return 0;
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if (strstr(drive->id->model, "E X A B Y T E N E S T"))
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enable_nest(drive);
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/* identification failed? */
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if (!drive->id_read) {
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@ -238,7 +238,7 @@ EXPORT_SYMBOL(task_no_data_intr);
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static u8 wait_drive_not_busy(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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int retries = 100;
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int retries;
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u8 stat;
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/*
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@ -246,10 +246,14 @@ static u8 wait_drive_not_busy(ide_drive_t *drive)
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* This can take up to 10 usec, but we will wait max 1 ms
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* (drive_cmd_intr() waits that long).
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*/
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while (((stat = hwif->INB(IDE_STATUS_REG)) & BUSY_STAT) && retries--)
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udelay(10);
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for (retries = 0; retries < 100; retries++) {
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if ((stat = hwif->INB(IDE_STATUS_REG)) & BUSY_STAT)
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udelay(10);
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else
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break;
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}
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if (!retries)
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if (stat & BUSY_STAT)
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printk(KERN_ERR "%s: drive still BUSY!\n", drive->name);
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return stat;
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@ -1,5 +1,5 @@
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/*
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* Version 2.15
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* Version 2.16
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*
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* AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
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* IDE driver for Linux.
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@ -244,10 +244,8 @@ static int amd_set_drive(ide_drive_t *drive, u8 speed)
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struct ide_timing t, p;
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int T, UT;
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if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
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if (ide_config_drive_speed(drive, speed))
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printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
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drive->dn >> 1, drive->dn & 1);
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if (speed != XFER_PIO_SLOW)
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ide_config_drive_speed(drive, speed);
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T = 1000000000 / amd_clock;
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UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2);
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@ -1,5 +1,5 @@
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/*
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* linux/drivers/ide/pci/hpt366.c Version 1.04 Jun 4, 2007
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* linux/drivers/ide/pci/hpt366.c Version 1.06 Jun 27, 2007
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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@ -182,6 +182,7 @@ static const char *bad_ata66_4[] = {
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"IC35L040AVER07-0",
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"IC35L060AVER07-0",
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"WDC AC310200R",
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"MAXTOR STM3320620A",
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NULL
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};
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@ -1513,18 +1514,28 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
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goto init_single;
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/*
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* HPT36x chips are single channel and
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* do not seem to have the channel enable bit...
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* HPT36x chips have one channel per function and have
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* both channel enable bits located differently and visible
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* to both functions -- really stupid design decision... :-(
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* Bit 4 is for the primary channel, bit 5 for the secondary.
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*/
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d->channels = 1;
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d->enablebits[0].reg = 0;
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d->enablebits[0].mask = d->enablebits[0].val = 0x10;
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if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
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u8 pin1 = 0, pin2 = 0;
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u8 mcr1 = 0, pin1 = 0, pin2 = 0;
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int ret;
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pci_set_drvdata(dev2, info[rev]);
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/*
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* Now we'll have to force both channels enabled if
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* at least one of them has been enabled by BIOS...
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*/
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pci_read_config_byte(dev, 0x50, &mcr1);
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if (mcr1 & 0x30)
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pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
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pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
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if (pin1 != pin2 && dev->irq == dev2->irq) {
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@ -1,6 +1,6 @@
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/*
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* linux/drivers/ide/pci/it821x.c Version 0.15 Jun 2 2007
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* linux/drivers/ide/pci/it821x.c Version 0.16 Jul 3 2007
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*
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* Copyright (C) 2004 Red Hat <alan@redhat.com>
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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@ -660,7 +660,6 @@ static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
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hwif->ultra_mask = 0x7f;
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hwif->mwdma_mask = 0x07;
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hwif->swdma_mask = 0x07;
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hwif->ide_dma_check = &it821x_config_drive_for_dma;
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if (!(hwif->udma_four))
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@ -306,11 +306,13 @@ static long __devinit read_counter(u32 dma_base)
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*/
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static long __devinit detect_pll_input_clock(unsigned long dma_base)
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{
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struct timeval start_time, end_time;
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long start_count, end_count;
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long pll_input;
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long pll_input, usec_elapsed;
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u8 scr1;
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start_count = read_counter(dma_base);
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do_gettimeofday(&start_time);
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/* Start the test mode */
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outb(0x01, dma_base + 0x01);
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@ -322,6 +324,7 @@ static long __devinit detect_pll_input_clock(unsigned long dma_base)
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mdelay(10);
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end_count = read_counter(dma_base);
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do_gettimeofday(&end_time);
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/* Stop the test mode */
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outb(0x01, dma_base + 0x01);
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@ -333,7 +336,10 @@ static long __devinit detect_pll_input_clock(unsigned long dma_base)
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* Calculate the input clock in Hz
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* (the clock counter is 30 bit wide and counts down)
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*/
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pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
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usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
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(end_time.tv_usec - start_time.tv_usec);
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pll_input = ((start_count - end_count) & 0x3ffffff) / 10 *
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(10000000 / usec_elapsed);
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DBG("start[%ld] end[%ld]\n", start_count, end_count);
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@ -872,11 +872,15 @@ void __init ide_scan_pcibus (int scan_direction)
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* are post init.
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*/
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list_for_each_safe(l, n, &ide_pci_drivers)
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{
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list_for_each_safe(l, n, &ide_pci_drivers) {
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list_del(l);
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d = list_entry(l, struct pci_driver, node);
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__pci_register_driver(d, d->driver.owner, d->driver.mod_name);
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if (__pci_register_driver(d, d->driver.owner,
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d->driver.mod_name)) {
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printk(KERN_ERR "%s: failed to register driver "
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"for %s\n", __FUNCTION__,
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d->driver.mod_name);
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}
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}
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}
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#endif
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