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Enable atomic64 ops in C6X

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- define L1_CACHE_SHIFT
   - select GENERIC_ATOMIC64
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Merge tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming

Pull C6X atomic64 support from Mark Salter:
 "Enable atomic64 ops in C6X
   - define L1_CACHE_SHIFT
   - select GENERIC_ATOMIC64"

* tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming:
  C6X: select GENERIC_ATOMIC64
  C6X: add Lx_CACHE_SHIFT defines
This commit is contained in:
Linus Torvalds 2012-08-17 08:10:12 -07:00
commit 9d0f8140fc
2 changed files with 12 additions and 5 deletions
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1
arch/c6x/Kconfig
View file

@ -6,6 +6,7 @@
config C6X
def_bool y
select CLKDEV_LOOKUP
select GENERIC_ATOMIC64
select GENERIC_IRQ_SHOW
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG

16
arch/c6x/include/asm/cache.h
View file

@ -1,7 +1,7 @@
/*
* Port on Texas Instruments TMS320C6x architecture
*
* Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
* Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
* Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
*
* This program is free software; you can redistribute it and/or modify
@ -16,9 +16,14 @@
/*
* Cache line size
*/
#define L1D_CACHE_BYTES 64
#define L1P_CACHE_BYTES 32
#define L2_CACHE_BYTES 128
#define L1D_CACHE_SHIFT 6
#define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT)
#define L1P_CACHE_SHIFT 5
#define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT)
#define L2_CACHE_SHIFT 7
#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
/*
* L2 used as cache
@ -29,7 +34,8 @@
* For practical reasons the L1_CACHE_BYTES defines should not be smaller than
* the L2 line size
*/
#define L1_CACHE_BYTES L2_CACHE_BYTES
#define L1_CACHE_SHIFT L2_CACHE_SHIFT
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define L2_CACHE_ALIGN_LOW(x) \
(((x) & ~(L2_CACHE_BYTES - 1)))