asoc: codecs: Tanggu TX RX changes
Tanggu codec driver changes for RX and TX widgets, dapm sequences and routes update. CRs-Fixed: 2281591 Change-Id: I769255e80c8569f7d954a5e5e5c62b8048d62b0b Signed-off-by: Tanya Dixit <tdixit@codeaurora.org>
This commit is contained in:
Tanya Dixit
parent
759426ec4b
commit
9b37ac95f1
6 changed files with 2526 additions and 24 deletions
asoc/codecs/wcd937x
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@ -52,6 +52,8 @@ COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
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# for WCD937X Codec
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ifdef CONFIG_SND_SOC_WCD937X
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WCD937X_OBJS += wcd937x.o
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WCD937X_OBJS += wcd937x-regmap.o
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WCD937X_OBJS += wcd937x-tables.o
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endif
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ifdef CONFIG_SND_SOC_WCD937X_SLAVE
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58
asoc/codecs/wcd937x/internal.h
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58
asoc/codecs/wcd937x/internal.h
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@ -0,0 +1,58 @@
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/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _WCD937X_INTERNAL_H
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#define _WCD937X_INTERNAL_H
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#include "../wcd-mbhc-v2.h"
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#define WCD937X_MAX_MICBIAS 3
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extern struct regmap_config wcd937x_regmap_config;
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struct wcd937x_priv {
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struct device *dev;
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int variant;
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struct snd_soc_codec *codec;
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struct device_node *rst_np;
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struct regmap *regmap;
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struct swr_device *rx_swr_dev;
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struct swr_device *tx_swr_dev;
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s32 micb_ref[WCD937X_MAX_MICBIAS];
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s32 pullup_ref[WCD937X_MAX_MICBIAS];
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struct fw_info *fw_data;
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struct device_node *wcd_rst_np;
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s32 dmic_0_1_clk_cnt;
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s32 dmic_2_3_clk_cnt;
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s32 dmic_4_5_clk_cnt;
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/* mbhc module */
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struct wcd_mbhc mbhc;
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struct blocking_notifier_head notifier;
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struct mutex micb_lock;
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u32 hph_mode;
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u32 rx_clk_cnt;
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};
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struct wcd937x_pdata {
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struct device_node *rst_np;
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struct device_node *rx_slave;
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struct device_node *tx_slave;
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};
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#endif
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446
asoc/codecs/wcd937x/wcd937x-registers.h
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446
asoc/codecs/wcd937x/wcd937x-registers.h
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@ -0,0 +1,446 @@
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _WCD937X_REGISTERS_H
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#define _WCD937X_REGISTERS_H
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#define WCD937X_BASE_ADDRESS 0x3000
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#define WCD937X_REG(reg) (reg - WCD937X_BASE_ADDRESS)
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enum {
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REG_NO_ACCESS,
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RD_REG,
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WR_REG,
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RD_WR_REG
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};
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#define WCD937X_ANA_BIAS (WCD937X_BASE_ADDRESS+0x001)
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#define WCD937X_ANA_RX_SUPPLIES (WCD937X_BASE_ADDRESS+0x008)
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#define WCD937X_ANA_HPH (WCD937X_BASE_ADDRESS+0x009)
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#define WCD937X_ANA_EAR (WCD937X_BASE_ADDRESS+0x00A)
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#define WCD937X_ANA_EAR_COMPANDER_CTL (WCD937X_BASE_ADDRESS+0x00B)
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#define WCD937X_ANA_TX_CH1 (WCD937X_BASE_ADDRESS+0x00E)
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#define WCD937X_ANA_TX_CH2 (WCD937X_BASE_ADDRESS+0x00F)
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#define WCD937X_ANA_TX_CH3 (WCD937X_BASE_ADDRESS+0x010)
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#define WCD937X_ANA_TX_CH3_HPF (WCD937X_BASE_ADDRESS+0x011)
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#define WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC (WCD937X_BASE_ADDRESS+0x012)
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#define WCD937X_ANA_MICB3_DSP_EN_LOGIC (WCD937X_BASE_ADDRESS+0x013)
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#define WCD937X_ANA_MBHC_MECH (WCD937X_BASE_ADDRESS+0x014)
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#define WCD937X_ANA_MBHC_ELECT (WCD937X_BASE_ADDRESS+0x015)
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#define WCD937X_ANA_MBHC_ZDET (WCD937X_BASE_ADDRESS+0x016)
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#define WCD937X_ANA_MBHC_RESULT_1 (WCD937X_BASE_ADDRESS+0x017)
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#define WCD937X_ANA_MBHC_RESULT_2 (WCD937X_BASE_ADDRESS+0x018)
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#define WCD937X_ANA_MBHC_RESULT_3 (WCD937X_BASE_ADDRESS+0x019)
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#define WCD937X_ANA_MBHC_BTN0 (WCD937X_BASE_ADDRESS+0x01A)
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#define WCD937X_ANA_MBHC_BTN1 (WCD937X_BASE_ADDRESS+0x01B)
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#define WCD937X_ANA_MBHC_BTN2 (WCD937X_BASE_ADDRESS+0x01C)
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#define WCD937X_ANA_MBHC_BTN3 (WCD937X_BASE_ADDRESS+0x01D)
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#define WCD937X_ANA_MBHC_BTN4 (WCD937X_BASE_ADDRESS+0x01E)
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#define WCD937X_ANA_MBHC_BTN5 (WCD937X_BASE_ADDRESS+0x01F)
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#define WCD937X_ANA_MBHC_BTN6 (WCD937X_BASE_ADDRESS+0x020)
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#define WCD937X_ANA_MBHC_BTN7 (WCD937X_BASE_ADDRESS+0x021)
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#define WCD937X_ANA_MICB1 (WCD937X_BASE_ADDRESS+0x022)
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#define WCD937X_ANA_MICB2 (WCD937X_BASE_ADDRESS+0x023)
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#define WCD937X_ANA_MICB2_RAMP (WCD937X_BASE_ADDRESS+0x024)
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#define WCD937X_ANA_MICB3 (WCD937X_BASE_ADDRESS+0x025)
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#define WCD937X_BIAS_CTL (WCD937X_BASE_ADDRESS+0x028)
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#define WCD937X_BIAS_VBG_FINE_ADJ (WCD937X_BASE_ADDRESS+0x029)
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#define WCD937X_LDOL_VDDCX_ADJUST (WCD937X_BASE_ADDRESS+0x040)
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#define WCD937X_LDOL_DISABLE_LDOL (WCD937X_BASE_ADDRESS+0x041)
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#define WCD937X_MBHC_CTL_CLK (WCD937X_BASE_ADDRESS+0x056)
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#define WCD937X_MBHC_CTL_ANA (WCD937X_BASE_ADDRESS+0x057)
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#define WCD937X_MBHC_CTL_SPARE_1 (WCD937X_BASE_ADDRESS+0x058)
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#define WCD937X_MBHC_CTL_SPARE_2 (WCD937X_BASE_ADDRESS+0x059)
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#define WCD937X_MBHC_CTL_BCS (WCD937X_BASE_ADDRESS+0x05A)
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#define WCD937X_MBHC_MOISTURE_DET_FSM_STATUS (WCD937X_BASE_ADDRESS+0x05B)
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#define WCD937X_MBHC_TEST_CTL (WCD937X_BASE_ADDRESS+0x05C)
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#define WCD937X_LDOH_MODE (WCD937X_BASE_ADDRESS+0x067)
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#define WCD937X_LDOH_BIAS (WCD937X_BASE_ADDRESS+0x068)
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#define WCD937X_LDOH_STB_LOADS (WCD937X_BASE_ADDRESS+0x069)
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#define WCD937X_LDOH_SLOWRAMP (WCD937X_BASE_ADDRESS+0x06A)
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#define WCD937X_MICB1_TEST_CTL_1 (WCD937X_BASE_ADDRESS+0x06B)
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#define WCD937X_MICB1_TEST_CTL_2 (WCD937X_BASE_ADDRESS+0x06C)
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#define WCD937X_MICB1_TEST_CTL_3 (WCD937X_BASE_ADDRESS+0x06D)
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#define WCD937X_MICB2_TEST_CTL_1 (WCD937X_BASE_ADDRESS+0x06E)
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#define WCD937X_MICB2_TEST_CTL_2 (WCD937X_BASE_ADDRESS+0x06F)
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#define WCD937X_MICB2_TEST_CTL_3 (WCD937X_BASE_ADDRESS+0x070)
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#define WCD937X_MICB3_TEST_CTL_1 (WCD937X_BASE_ADDRESS+0x071)
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#define WCD937X_MICB3_TEST_CTL_2 (WCD937X_BASE_ADDRESS+0x072)
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#define WCD937X_MICB3_TEST_CTL_3 (WCD937X_BASE_ADDRESS+0x073)
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#define WCD937X_TX_COM_ADC_VCM (WCD937X_BASE_ADDRESS+0x077)
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#define WCD937X_TX_COM_BIAS_ATEST (WCD937X_BASE_ADDRESS+0x078)
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#define WCD937X_TX_COM_ADC_INT1_IB (WCD937X_BASE_ADDRESS+0x079)
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#define WCD937X_TX_COM_ADC_INT2_IB (WCD937X_BASE_ADDRESS+0x07A)
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#define WCD937X_TX_COM_TXFE_DIV_CTL (WCD937X_BASE_ADDRESS+0x07B)
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#define WCD937X_TX_COM_TXFE_DIV_START (WCD937X_BASE_ADDRESS+0x07C)
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#define WCD937X_TX_COM_TXFE_DIV_STOP_9P6M (WCD937X_BASE_ADDRESS+0x07D)
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#define WCD937X_TX_COM_TXFE_DIV_STOP_12P288M (WCD937X_BASE_ADDRESS+0x07E)
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#define WCD937X_TX_1_2_TEST_EN (WCD937X_BASE_ADDRESS+0x07F)
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#define WCD937X_TX_1_2_ADC_IB (WCD937X_BASE_ADDRESS+0x080)
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#define WCD937X_TX_1_2_ATEST_REFCTL (WCD937X_BASE_ADDRESS+0x081)
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#define WCD937X_TX_1_2_TEST_CTL (WCD937X_BASE_ADDRESS+0x082)
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#define WCD937X_TX_1_2_TEST_BLK_EN (WCD937X_BASE_ADDRESS+0x083)
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#define WCD937X_TX_1_2_TXFE_CLKDIV (WCD937X_BASE_ADDRESS+0x084)
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#define WCD937X_TX_1_2_SAR2_ERR (WCD937X_BASE_ADDRESS+0x085)
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#define WCD937X_TX_1_2_SAR1_ERR (WCD937X_BASE_ADDRESS+0x086)
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#define WCD937X_TX_3_TEST_EN (WCD937X_BASE_ADDRESS+0x087)
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#define WCD937X_TX_3_ADC_IB (WCD937X_BASE_ADDRESS+0x088)
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#define WCD937X_TX_3_ATEST_REFCTL (WCD937X_BASE_ADDRESS+0x089)
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#define WCD937X_TX_3_TEST_CTL (WCD937X_BASE_ADDRESS+0x08A)
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#define WCD937X_TX_3_TEST_BLK_EN (WCD937X_BASE_ADDRESS+0x08B)
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#define WCD937X_TX_3_TXFE_CLKDIV (WCD937X_BASE_ADDRESS+0x08C)
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#define WCD937X_TX_3_SPARE_MONO (WCD937X_BASE_ADDRESS+0x08D)
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#define WCD937X_TX_3_SAR1_ERR (WCD937X_BASE_ADDRESS+0x08E)
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#define WCD937X_CLASSH_MODE_1 (WCD937X_BASE_ADDRESS+0x097)
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#define WCD937X_CLASSH_MODE_2 (WCD937X_BASE_ADDRESS+0x098)
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#define WCD937X_CLASSH_MODE_3 (WCD937X_BASE_ADDRESS+0x099)
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#define WCD937X_CLASSH_CTRL_VCL_1 (WCD937X_BASE_ADDRESS+0x09A)
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#define WCD937X_CLASSH_CTRL_VCL_2 (WCD937X_BASE_ADDRESS+0x09B)
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#define WCD937X_CLASSH_CTRL_CCL_1 (WCD937X_BASE_ADDRESS+0x09C)
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#define WCD937X_CLASSH_CTRL_CCL_2 (WCD937X_BASE_ADDRESS+0x09D)
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#define WCD937X_CLASSH_CTRL_CCL_3 (WCD937X_BASE_ADDRESS+0x09E)
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#define WCD937X_CLASSH_CTRL_CCL_4 (WCD937X_BASE_ADDRESS+0x09F)
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#define WCD937X_CLASSH_CTRL_CCL_5 (WCD937X_BASE_ADDRESS+0x0A0)
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#define WCD937X_CLASSH_BUCK_TMUX_A_D (WCD937X_BASE_ADDRESS+0x0A1)
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#define WCD937X_CLASSH_BUCK_SW_DRV_CNTL (WCD937X_BASE_ADDRESS+0x0A2)
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#define WCD937X_CLASSH_SPARE (WCD937X_BASE_ADDRESS+0x0A3)
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#define WCD937X_FLYBACK_EN (WCD937X_BASE_ADDRESS+0x0A4)
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#define WCD937X_FLYBACK_VNEG_CTRL_1 (WCD937X_BASE_ADDRESS+0x0A5)
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#define WCD937X_FLYBACK_VNEG_CTRL_2 (WCD937X_BASE_ADDRESS+0x0A6)
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#define WCD937X_FLYBACK_VNEG_CTRL_3 (WCD937X_BASE_ADDRESS+0x0A7)
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#define WCD937X_FLYBACK_VNEG_CTRL_4 (WCD937X_BASE_ADDRESS+0x0A8)
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#define WCD937X_FLYBACK_VNEG_CTRL_5 (WCD937X_BASE_ADDRESS+0x0A9)
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#define WCD937X_FLYBACK_VNEG_CTRL_6 (WCD937X_BASE_ADDRESS+0x0AA)
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#define WCD937X_FLYBACK_VNEG_CTRL_7 (WCD937X_BASE_ADDRESS+0x0AB)
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#define WCD937X_FLYBACK_VNEG_CTRL_8 (WCD937X_BASE_ADDRESS+0x0AC)
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#define WCD937X_FLYBACK_VNEG_CTRL_9 (WCD937X_BASE_ADDRESS+0x0AD)
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#define WCD937X_FLYBACK_VNEGDAC_CTRL_1 (WCD937X_BASE_ADDRESS+0x0AE)
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#define WCD937X_FLYBACK_VNEGDAC_CTRL_2 (WCD937X_BASE_ADDRESS+0x0AF)
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#define WCD937X_FLYBACK_VNEGDAC_CTRL_3 (WCD937X_BASE_ADDRESS+0x0B0)
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#define WCD937X_FLYBACK_CTRL_1 (WCD937X_BASE_ADDRESS+0x0B1)
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#define WCD937X_FLYBACK_TEST_CTL (WCD937X_BASE_ADDRESS+0x0B2)
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#define WCD937X_RX_AUX_SW_CTL (WCD937X_BASE_ADDRESS+0x0B3)
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#define WCD937X_RX_PA_AUX_IN_CONN (WCD937X_BASE_ADDRESS+0x0B4)
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#define WCD937X_RX_TIMER_DIV (WCD937X_BASE_ADDRESS+0x0B5)
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#define WCD937X_RX_OCP_CTL (WCD937X_BASE_ADDRESS+0x0B6)
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#define WCD937X_RX_OCP_COUNT (WCD937X_BASE_ADDRESS+0x0B7)
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#define WCD937X_RX_BIAS_EAR_DAC (WCD937X_BASE_ADDRESS+0x0B8)
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#define WCD937X_RX_BIAS_EAR_AMP (WCD937X_BASE_ADDRESS+0x0B9)
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#define WCD937X_RX_BIAS_HPH_LDO (WCD937X_BASE_ADDRESS+0x0BA)
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#define WCD937X_RX_BIAS_HPH_PA (WCD937X_BASE_ADDRESS+0x0BB)
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#define WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2 (WCD937X_BASE_ADDRESS+0x0BC)
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#define WCD937X_RX_BIAS_HPH_RDAC_LDO (WCD937X_BASE_ADDRESS+0x0BD)
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#define WCD937X_RX_BIAS_HPH_CNP1 (WCD937X_BASE_ADDRESS+0x0BE)
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#define WCD937X_RX_BIAS_HPH_LOWPOWER (WCD937X_BASE_ADDRESS+0x0BF)
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#define WCD937X_RX_BIAS_AUX_DAC (WCD937X_BASE_ADDRESS+0x0C0)
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#define WCD937X_RX_BIAS_AUX_AMP (WCD937X_BASE_ADDRESS+0x0C1)
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#define WCD937X_RX_BIAS_VNEGDAC_BLEEDER (WCD937X_BASE_ADDRESS+0x0C2)
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#define WCD937X_RX_BIAS_MISC (WCD937X_BASE_ADDRESS+0x0C3)
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#define WCD937X_RX_BIAS_BUCK_RST (WCD937X_BASE_ADDRESS+0x0C4)
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#define WCD937X_RX_BIAS_BUCK_VREF_ERRAMP (WCD937X_BASE_ADDRESS+0x0C5)
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#define WCD937X_RX_BIAS_FLYB_ERRAMP (WCD937X_BASE_ADDRESS+0x0C6)
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#define WCD937X_RX_BIAS_FLYB_BUFF (WCD937X_BASE_ADDRESS+0x0C7)
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#define WCD937X_RX_BIAS_FLYB_MID_RST (WCD937X_BASE_ADDRESS+0x0C8)
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#define WCD937X_HPH_L_STATUS (WCD937X_BASE_ADDRESS+0x0C9)
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#define WCD937X_HPH_R_STATUS (WCD937X_BASE_ADDRESS+0x0CA)
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#define WCD937X_HPH_CNP_EN (WCD937X_BASE_ADDRESS+0x0CB)
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#define WCD937X_HPH_CNP_WG_CTL (WCD937X_BASE_ADDRESS+0x0CC)
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#define WCD937X_HPH_CNP_WG_TIME (WCD937X_BASE_ADDRESS+0x0CD)
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#define WCD937X_HPH_OCP_CTL (WCD937X_BASE_ADDRESS+0x0CE)
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#define WCD937X_HPH_AUTO_CHOP (WCD937X_BASE_ADDRESS+0x0CF)
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#define WCD937X_HPH_CHOP_CTL (WCD937X_BASE_ADDRESS+0x0D0)
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#define WCD937X_HPH_PA_CTL1 (WCD937X_BASE_ADDRESS+0x0D1)
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#define WCD937X_HPH_PA_CTL2 (WCD937X_BASE_ADDRESS+0x0D2)
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#define WCD937X_HPH_L_EN (WCD937X_BASE_ADDRESS+0x0D3)
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#define WCD937X_HPH_L_TEST (WCD937X_BASE_ADDRESS+0x0D4)
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#define WCD937X_HPH_L_ATEST (WCD937X_BASE_ADDRESS+0x0D5)
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#define WCD937X_HPH_R_EN (WCD937X_BASE_ADDRESS+0x0D6)
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#define WCD937X_HPH_R_TEST (WCD937X_BASE_ADDRESS+0x0D7)
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#define WCD937X_HPH_R_ATEST (WCD937X_BASE_ADDRESS+0x0D8)
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#define WCD937X_HPH_RDAC_CLK_CTL1 (WCD937X_BASE_ADDRESS+0x0D9)
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#define WCD937X_HPH_RDAC_CLK_CTL2 (WCD937X_BASE_ADDRESS+0x0DA)
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#define WCD937X_HPH_RDAC_LDO_CTL (WCD937X_BASE_ADDRESS+0x0DB)
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#define WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL (WCD937X_BASE_ADDRESS+0x0DC)
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#define WCD937X_HPH_REFBUFF_UHQA_CTL (WCD937X_BASE_ADDRESS+0x0DD)
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#define WCD937X_HPH_REFBUFF_LP_CTL (WCD937X_BASE_ADDRESS+0x0DE)
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#define WCD937X_HPH_L_DAC_CTL (WCD937X_BASE_ADDRESS+0x0DF)
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#define WCD937X_HPH_R_DAC_CTL (WCD937X_BASE_ADDRESS+0x0E0)
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#define WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL (WCD937X_BASE_ADDRESS+0x0E1)
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#define WCD937X_HPH_SURGE_HPHLR_SURGE_EN (WCD937X_BASE_ADDRESS+0x0E2)
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#define WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1 (WCD937X_BASE_ADDRESS+0x0E3)
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#define WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS (WCD937X_BASE_ADDRESS+0x0E4)
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#define WCD937X_EAR_EAR_EN_REG (WCD937X_BASE_ADDRESS+0x0E9)
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#define WCD937X_EAR_EAR_PA_CON (WCD937X_BASE_ADDRESS+0x0EA)
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#define WCD937X_EAR_EAR_SP_CON (WCD937X_BASE_ADDRESS+0x0EB)
|
||||
#define WCD937X_EAR_EAR_DAC_CON (WCD937X_BASE_ADDRESS+0x0EC)
|
||||
#define WCD937X_EAR_EAR_CNP_FSM_CON (WCD937X_BASE_ADDRESS+0x0ED)
|
||||
#define WCD937X_EAR_TEST_CTL (WCD937X_BASE_ADDRESS+0x0EE)
|
||||
#define WCD937X_EAR_STATUS_REG_1 (WCD937X_BASE_ADDRESS+0x0EF)
|
||||
#define WCD937X_EAR_STATUS_REG_2 (WCD937X_BASE_ADDRESS+0x0F0)
|
||||
#define WCD937X_ANA_NEW_PAGE_REGISTER (WCD937X_BASE_ADDRESS+0x100)
|
||||
#define WCD937X_HPH_NEW_ANA_HPH2 (WCD937X_BASE_ADDRESS+0x101)
|
||||
#define WCD937X_HPH_NEW_ANA_HPH3 (WCD937X_BASE_ADDRESS+0x102)
|
||||
#define WCD937X_SLEEP_CTL (WCD937X_BASE_ADDRESS+0x103)
|
||||
#define WCD937X_SLEEP_WATCHDOG_CTL (WCD937X_BASE_ADDRESS+0x104)
|
||||
#define WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL (WCD937X_BASE_ADDRESS+0x11F)
|
||||
#define WCD937X_MBHC_NEW_CTL_1 (WCD937X_BASE_ADDRESS+0x120)
|
||||
#define WCD937X_MBHC_NEW_CTL_2 (WCD937X_BASE_ADDRESS+0x121)
|
||||
#define WCD937X_MBHC_NEW_PLUG_DETECT_CTL (WCD937X_BASE_ADDRESS+0x122)
|
||||
#define WCD937X_MBHC_NEW_ZDET_ANA_CTL (WCD937X_BASE_ADDRESS+0x123)
|
||||
#define WCD937X_MBHC_NEW_ZDET_RAMP_CTL (WCD937X_BASE_ADDRESS+0x124)
|
||||
#define WCD937X_MBHC_NEW_FSM_STATUS (WCD937X_BASE_ADDRESS+0x125)
|
||||
#define WCD937X_MBHC_NEW_ADC_RESULT (WCD937X_BASE_ADDRESS+0x126)
|
||||
#define WCD937X_TX_NEW_TX_CH2_SEL (WCD937X_BASE_ADDRESS+0x127)
|
||||
#define WCD937X_AUX_AUXPA (WCD937X_BASE_ADDRESS+0x128)
|
||||
#define WCD937X_LDORXTX_MODE (WCD937X_BASE_ADDRESS+0x129)
|
||||
#define WCD937X_LDORXTX_CONFIG (WCD937X_BASE_ADDRESS+0x12A)
|
||||
#define WCD937X_DIE_CRACK_DIE_CRK_DET_EN (WCD937X_BASE_ADDRESS+0x12C)
|
||||
#define WCD937X_DIE_CRACK_DIE_CRK_DET_OUT (WCD937X_BASE_ADDRESS+0x12D)
|
||||
#define WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL (WCD937X_BASE_ADDRESS+0x132)
|
||||
#define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L (WCD937X_BASE_ADDRESS+0x133)
|
||||
#define WCD937X_HPH_NEW_INT_RDAC_VREF_CTL (WCD937X_BASE_ADDRESS+0x134)
|
||||
#define WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL (WCD937X_BASE_ADDRESS+0x135)
|
||||
#define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R (WCD937X_BASE_ADDRESS+0x136)
|
||||
#define WCD937X_HPH_NEW_INT_PA_MISC1 (WCD937X_BASE_ADDRESS+0x137)
|
||||
#define WCD937X_HPH_NEW_INT_PA_MISC2 (WCD937X_BASE_ADDRESS+0x138)
|
||||
#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC (WCD937X_BASE_ADDRESS+0x139)
|
||||
#define WCD937X_HPH_NEW_INT_HPH_TIMER1 (WCD937X_BASE_ADDRESS+0x13A)
|
||||
#define WCD937X_HPH_NEW_INT_HPH_TIMER2 (WCD937X_BASE_ADDRESS+0x13B)
|
||||
#define WCD937X_HPH_NEW_INT_HPH_TIMER3 (WCD937X_BASE_ADDRESS+0x13C)
|
||||
#define WCD937X_HPH_NEW_INT_HPH_TIMER4 (WCD937X_BASE_ADDRESS+0x13D)
|
||||
#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC2 (WCD937X_BASE_ADDRESS+0x13E)
|
||||
#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC3 (WCD937X_BASE_ADDRESS+0x13F)
|
||||
#define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (WCD937X_BASE_ADDRESS+0x145)
|
||||
#define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP (WCD937X_BASE_ADDRESS+0x146)
|
||||
#define WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP (WCD937X_BASE_ADDRESS+0x147)
|
||||
#define WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (WCD937X_BASE_ADDRESS+0x1AF)
|
||||
#define WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL \
|
||||
(WCD937X_BASE_ADDRESS+0x1B0)
|
||||
#define WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT (WCD937X_BASE_ADDRESS+0x1B1)
|
||||
#define WCD937X_MBHC_NEW_INT_SPARE_2 (WCD937X_BASE_ADDRESS+0x1B2)
|
||||
#define WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON (WCD937X_BASE_ADDRESS+0x1B7)
|
||||
#define WCD937X_EAR_INT_NEW_CNP_VCM_CON1 (WCD937X_BASE_ADDRESS+0x1B8)
|
||||
#define WCD937X_EAR_INT_NEW_CNP_VCM_CON2 (WCD937X_BASE_ADDRESS+0x1B9)
|
||||
#define WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS (WCD937X_BASE_ADDRESS+0x1BA)
|
||||
#define WCD937X_AUX_INT_EN_REG (WCD937X_BASE_ADDRESS+0x1BD)
|
||||
#define WCD937X_AUX_INT_PA_CTRL (WCD937X_BASE_ADDRESS+0x1BE)
|
||||
#define WCD937X_AUX_INT_SP_CTRL (WCD937X_BASE_ADDRESS+0x1BF)
|
||||
#define WCD937X_AUX_INT_DAC_CTRL (WCD937X_BASE_ADDRESS+0x1C0)
|
||||
#define WCD937X_AUX_INT_CLK_CTRL (WCD937X_BASE_ADDRESS+0x1C1)
|
||||
#define WCD937X_AUX_INT_TEST_CTRL (WCD937X_BASE_ADDRESS+0x1C2)
|
||||
#define WCD937X_AUX_INT_STATUS_REG (WCD937X_BASE_ADDRESS+0x1C3)
|
||||
#define WCD937X_AUX_INT_MISC (WCD937X_BASE_ADDRESS+0x1C4)
|
||||
#define WCD937X_LDORXTX_INT_BIAS (WCD937X_BASE_ADDRESS+0x1C5)
|
||||
#define WCD937X_LDORXTX_INT_STB_LOADS_DTEST (WCD937X_BASE_ADDRESS+0x1C6)
|
||||
#define WCD937X_LDORXTX_INT_TEST0 (WCD937X_BASE_ADDRESS+0x1C7)
|
||||
#define WCD937X_LDORXTX_INT_STARTUP_TIMER (WCD937X_BASE_ADDRESS+0x1C8)
|
||||
#define WCD937X_LDORXTX_INT_TEST1 (WCD937X_BASE_ADDRESS+0x1C9)
|
||||
#define WCD937X_LDORXTX_INT_STATUS (WCD937X_BASE_ADDRESS+0x1CA)
|
||||
#define WCD937X_SLEEP_INT_WATCHDOG_CTL_1 (WCD937X_BASE_ADDRESS+0x1D0)
|
||||
#define WCD937X_SLEEP_INT_WATCHDOG_CTL_2 (WCD937X_BASE_ADDRESS+0x1D1)
|
||||
#define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1 (WCD937X_BASE_ADDRESS+0x1D3)
|
||||
#define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2 (WCD937X_BASE_ADDRESS+0x1D4)
|
||||
#define WCD937X_DIGITAL_PAGE_REGISTER (WCD937X_BASE_ADDRESS+0x400)
|
||||
#define WCD937X_DIGITAL_CHIP_ID0 (WCD937X_BASE_ADDRESS+0x401)
|
||||
#define WCD937X_DIGITAL_CHIP_ID1 (WCD937X_BASE_ADDRESS+0x402)
|
||||
#define WCD937X_DIGITAL_CHIP_ID2 (WCD937X_BASE_ADDRESS+0x403)
|
||||
#define WCD937X_DIGITAL_CHIP_ID3 (WCD937X_BASE_ADDRESS+0x404)
|
||||
#define WCD937X_DIGITAL_CDC_RST_CTL (WCD937X_BASE_ADDRESS+0x406)
|
||||
#define WCD937X_DIGITAL_TOP_CLK_CFG (WCD937X_BASE_ADDRESS+0x407)
|
||||
#define WCD937X_DIGITAL_CDC_ANA_CLK_CTL (WCD937X_BASE_ADDRESS+0x408)
|
||||
#define WCD937X_DIGITAL_CDC_DIG_CLK_CTL (WCD937X_BASE_ADDRESS+0x409)
|
||||
#define WCD937X_DIGITAL_SWR_RST_EN (WCD937X_BASE_ADDRESS+0x40A)
|
||||
#define WCD937X_DIGITAL_CDC_PATH_MODE (WCD937X_BASE_ADDRESS+0x40B)
|
||||
#define WCD937X_DIGITAL_CDC_RX_RST (WCD937X_BASE_ADDRESS+0x40C)
|
||||
#define WCD937X_DIGITAL_CDC_RX0_CTL (WCD937X_BASE_ADDRESS+0x40D)
|
||||
#define WCD937X_DIGITAL_CDC_RX1_CTL (WCD937X_BASE_ADDRESS+0x40E)
|
||||
#define WCD937X_DIGITAL_CDC_RX2_CTL (WCD937X_BASE_ADDRESS+0x40F)
|
||||
#define WCD937X_DIGITAL_DEM_BYPASS_DATA0 (WCD937X_BASE_ADDRESS+0x410)
|
||||
#define WCD937X_DIGITAL_DEM_BYPASS_DATA1 (WCD937X_BASE_ADDRESS+0x411)
|
||||
#define WCD937X_DIGITAL_DEM_BYPASS_DATA2 (WCD937X_BASE_ADDRESS+0x412)
|
||||
#define WCD937X_DIGITAL_DEM_BYPASS_DATA3 (WCD937X_BASE_ADDRESS+0x413)
|
||||
#define WCD937X_DIGITAL_CDC_COMP_CTL_0 (WCD937X_BASE_ADDRESS+0x414)
|
||||
#define WCD937X_DIGITAL_CDC_RX_DELAY_CTL (WCD937X_BASE_ADDRESS+0x417)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A1_0 (WCD937X_BASE_ADDRESS+0x418)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A1_1 (WCD937X_BASE_ADDRESS+0x419)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A2_0 (WCD937X_BASE_ADDRESS+0x41A)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A2_1 (WCD937X_BASE_ADDRESS+0x41B)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A3_0 (WCD937X_BASE_ADDRESS+0x41C)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A3_1 (WCD937X_BASE_ADDRESS+0x41D)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A4_0 (WCD937X_BASE_ADDRESS+0x41E)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A4_1 (WCD937X_BASE_ADDRESS+0x41F)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A5_0 (WCD937X_BASE_ADDRESS+0x420)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A5_1 (WCD937X_BASE_ADDRESS+0x421)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A6_0 (WCD937X_BASE_ADDRESS+0x422)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_A7_0 (WCD937X_BASE_ADDRESS+0x423)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_C_0 (WCD937X_BASE_ADDRESS+0x424)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_C_1 (WCD937X_BASE_ADDRESS+0x425)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_C_2 (WCD937X_BASE_ADDRESS+0x426)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_C_3 (WCD937X_BASE_ADDRESS+0x427)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_R1 (WCD937X_BASE_ADDRESS+0x428)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_R2 (WCD937X_BASE_ADDRESS+0x429)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_R3 (WCD937X_BASE_ADDRESS+0x42A)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_R4 (WCD937X_BASE_ADDRESS+0x42B)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_R5 (WCD937X_BASE_ADDRESS+0x42C)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_R6 (WCD937X_BASE_ADDRESS+0x42D)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_DSM_R7 (WCD937X_BASE_ADDRESS+0x42E)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A1_0 (WCD937X_BASE_ADDRESS+0x42F)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A1_1 (WCD937X_BASE_ADDRESS+0x430)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A2_0 (WCD937X_BASE_ADDRESS+0x431)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A2_1 (WCD937X_BASE_ADDRESS+0x432)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A3_0 (WCD937X_BASE_ADDRESS+0x433)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A3_1 (WCD937X_BASE_ADDRESS+0x434)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A4_0 (WCD937X_BASE_ADDRESS+0x435)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A4_1 (WCD937X_BASE_ADDRESS+0x436)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A5_0 (WCD937X_BASE_ADDRESS+0x437)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A5_1 (WCD937X_BASE_ADDRESS+0x438)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A6_0 (WCD937X_BASE_ADDRESS+0x439)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_A7_0 (WCD937X_BASE_ADDRESS+0x43A)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_C_0 (WCD937X_BASE_ADDRESS+0x43B)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_C_1 (WCD937X_BASE_ADDRESS+0x43C)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_C_2 (WCD937X_BASE_ADDRESS+0x43D)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_C_3 (WCD937X_BASE_ADDRESS+0x43E)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_R1 (WCD937X_BASE_ADDRESS+0x43F)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_R2 (WCD937X_BASE_ADDRESS+0x440)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_R3 (WCD937X_BASE_ADDRESS+0x441)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_R4 (WCD937X_BASE_ADDRESS+0x442)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_R5 (WCD937X_BASE_ADDRESS+0x443)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_R6 (WCD937X_BASE_ADDRESS+0x444)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_DSM_R7 (WCD937X_BASE_ADDRESS+0x445)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0 (WCD937X_BASE_ADDRESS+0x446)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1 (WCD937X_BASE_ADDRESS+0x447)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0 (WCD937X_BASE_ADDRESS+0x448)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1 (WCD937X_BASE_ADDRESS+0x449)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2 (WCD937X_BASE_ADDRESS+0x44A)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0 (WCD937X_BASE_ADDRESS+0x44B)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1 (WCD937X_BASE_ADDRESS+0x44C)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2 (WCD937X_BASE_ADDRESS+0x44D)
|
||||
#define WCD937X_DIGITAL_CDC_HPH_GAIN_CTL (WCD937X_BASE_ADDRESS+0x44E)
|
||||
#define WCD937X_DIGITAL_CDC_AUX_GAIN_CTL (WCD937X_BASE_ADDRESS+0x44F)
|
||||
#define WCD937X_DIGITAL_CDC_EAR_PATH_CTL (WCD937X_BASE_ADDRESS+0x450)
|
||||
#define WCD937X_DIGITAL_CDC_SWR_CLH (WCD937X_BASE_ADDRESS+0x451)
|
||||
#define WCD937X_DIGITAL_SWR_CLH_BYP (WCD937X_BASE_ADDRESS+0x452)
|
||||
#define WCD937X_DIGITAL_CDC_TX0_CTL (WCD937X_BASE_ADDRESS+0x453)
|
||||
#define WCD937X_DIGITAL_CDC_TX1_CTL (WCD937X_BASE_ADDRESS+0x454)
|
||||
#define WCD937X_DIGITAL_CDC_TX2_CTL (WCD937X_BASE_ADDRESS+0x455)
|
||||
#define WCD937X_DIGITAL_CDC_TX_RST (WCD937X_BASE_ADDRESS+0x456)
|
||||
#define WCD937X_DIGITAL_CDC_REQ_CTL (WCD937X_BASE_ADDRESS+0x457)
|
||||
#define WCD937X_DIGITAL_CDC_AMIC_CTL (WCD937X_BASE_ADDRESS+0x45A)
|
||||
#define WCD937X_DIGITAL_CDC_DMIC_CTL (WCD937X_BASE_ADDRESS+0x45B)
|
||||
#define WCD937X_DIGITAL_CDC_DMIC0_CTL (WCD937X_BASE_ADDRESS+0x45C)
|
||||
#define WCD937X_DIGITAL_CDC_DMIC1_CTL (WCD937X_BASE_ADDRESS+0x45D)
|
||||
#define WCD937X_DIGITAL_CDC_DMIC2_CTL (WCD937X_BASE_ADDRESS+0x45E)
|
||||
#define WCD937X_DIGITAL_EFUSE_CTL (WCD937X_BASE_ADDRESS+0x45F)
|
||||
#define WCD937X_DIGITAL_EFUSE_PRG_CTL (WCD937X_BASE_ADDRESS+0x460)
|
||||
#define WCD937X_DIGITAL_EFUSE_TEST_CTL_0 (WCD937X_BASE_ADDRESS+0x461)
|
||||
#define WCD937X_DIGITAL_EFUSE_TEST_CTL_1 (WCD937X_BASE_ADDRESS+0x462)
|
||||
#define WCD937X_DIGITAL_EFUSE_T_DATA_0 (WCD937X_BASE_ADDRESS+0x463)
|
||||
#define WCD937X_DIGITAL_EFUSE_T_DATA_1 (WCD937X_BASE_ADDRESS+0x464)
|
||||
#define WCD937X_DIGITAL_PDM_WD_CTL0 (WCD937X_BASE_ADDRESS+0x465)
|
||||
#define WCD937X_DIGITAL_PDM_WD_CTL1 (WCD937X_BASE_ADDRESS+0x466)
|
||||
#define WCD937X_DIGITAL_PDM_WD_CTL2 (WCD937X_BASE_ADDRESS+0x467)
|
||||
#define WCD937X_DIGITAL_INTR_MODE (WCD937X_BASE_ADDRESS+0x46A)
|
||||
#define WCD937X_DIGITAL_INTR_MASK_0 (WCD937X_BASE_ADDRESS+0x46B)
|
||||
#define WCD937X_DIGITAL_INTR_MASK_1 (WCD937X_BASE_ADDRESS+0x46C)
|
||||
#define WCD937X_DIGITAL_INTR_MASK_2 (WCD937X_BASE_ADDRESS+0x46D)
|
||||
#define WCD937X_DIGITAL_INTR_STATUS_0 (WCD937X_BASE_ADDRESS+0x46E)
|
||||
#define WCD937X_DIGITAL_INTR_STATUS_1 (WCD937X_BASE_ADDRESS+0x46F)
|
||||
#define WCD937X_DIGITAL_INTR_STATUS_2 (WCD937X_BASE_ADDRESS+0x470)
|
||||
#define WCD937X_DIGITAL_INTR_CLEAR_0 (WCD937X_BASE_ADDRESS+0x471)
|
||||
#define WCD937X_DIGITAL_INTR_CLEAR_1 (WCD937X_BASE_ADDRESS+0x472)
|
||||
#define WCD937X_DIGITAL_INTR_CLEAR_2 (WCD937X_BASE_ADDRESS+0x473)
|
||||
#define WCD937X_DIGITAL_INTR_LEVEL_0 (WCD937X_BASE_ADDRESS+0x474)
|
||||
#define WCD937X_DIGITAL_INTR_LEVEL_1 (WCD937X_BASE_ADDRESS+0x475)
|
||||
#define WCD937X_DIGITAL_INTR_LEVEL_2 (WCD937X_BASE_ADDRESS+0x476)
|
||||
#define WCD937X_DIGITAL_INTR_SET_0 (WCD937X_BASE_ADDRESS+0x477)
|
||||
#define WCD937X_DIGITAL_INTR_SET_1 (WCD937X_BASE_ADDRESS+0x478)
|
||||
#define WCD937X_DIGITAL_INTR_SET_2 (WCD937X_BASE_ADDRESS+0x479)
|
||||
#define WCD937X_DIGITAL_INTR_TEST_0 (WCD937X_BASE_ADDRESS+0x47A)
|
||||
#define WCD937X_DIGITAL_INTR_TEST_1 (WCD937X_BASE_ADDRESS+0x47B)
|
||||
#define WCD937X_DIGITAL_INTR_TEST_2 (WCD937X_BASE_ADDRESS+0x47C)
|
||||
#define WCD937X_DIGITAL_CDC_CONN_RX0_CTL (WCD937X_BASE_ADDRESS+0x47F)
|
||||
#define WCD937X_DIGITAL_CDC_CONN_RX1_CTL (WCD937X_BASE_ADDRESS+0x480)
|
||||
#define WCD937X_DIGITAL_CDC_CONN_RX2_CTL (WCD937X_BASE_ADDRESS+0x481)
|
||||
#define WCD937X_DIGITAL_CDC_CONN_TX_CTL (WCD937X_BASE_ADDRESS+0x482)
|
||||
#define WCD937X_DIGITAL_LOOP_BACK_MODE (WCD937X_BASE_ADDRESS+0x483)
|
||||
#define WCD937X_DIGITAL_SWR_DAC_TEST (WCD937X_BASE_ADDRESS+0x484)
|
||||
#define WCD937X_DIGITAL_SWR_HM_TEST_RX_0 (WCD937X_BASE_ADDRESS+0x485)
|
||||
#define WCD937X_DIGITAL_SWR_HM_TEST_TX_0 (WCD937X_BASE_ADDRESS+0x491)
|
||||
#define WCD937X_DIGITAL_SWR_HM_TEST_RX_1 (WCD937X_BASE_ADDRESS+0x492)
|
||||
#define WCD937X_DIGITAL_SWR_HM_TEST_TX_1 (WCD937X_BASE_ADDRESS+0x493)
|
||||
#define WCD937X_DIGITAL_SWR_HM_TEST (WCD937X_BASE_ADDRESS+0x494)
|
||||
#define WCD937X_DIGITAL_PAD_CTL_PDM_RX0 (WCD937X_BASE_ADDRESS+0x495)
|
||||
#define WCD937X_DIGITAL_PAD_CTL_PDM_RX1 (WCD937X_BASE_ADDRESS+0x496)
|
||||
#define WCD937X_DIGITAL_PAD_CTL_PDM_RX2 (WCD937X_BASE_ADDRESS+0x497)
|
||||
#define WCD937X_DIGITAL_PAD_CTL_PDM_TX (WCD937X_BASE_ADDRESS+0x498)
|
||||
#define WCD937X_DIGITAL_PAD_INP_DIS_0 (WCD937X_BASE_ADDRESS+0x499)
|
||||
#define WCD937X_DIGITAL_PAD_INP_DIS_1 (WCD937X_BASE_ADDRESS+0x49A)
|
||||
#define WCD937X_DIGITAL_DRIVE_STRENGTH_0 (WCD937X_BASE_ADDRESS+0x49B)
|
||||
#define WCD937X_DIGITAL_DRIVE_STRENGTH_1 (WCD937X_BASE_ADDRESS+0x49C)
|
||||
#define WCD937X_DIGITAL_DRIVE_STRENGTH_2 (WCD937X_BASE_ADDRESS+0x49D)
|
||||
#define WCD937X_DIGITAL_RX_DATA_EDGE_CTL (WCD937X_BASE_ADDRESS+0x49E)
|
||||
#define WCD937X_DIGITAL_TX_DATA_EDGE_CTL (WCD937X_BASE_ADDRESS+0x49F)
|
||||
#define WCD937X_DIGITAL_GPIO_MODE (WCD937X_BASE_ADDRESS+0x4A0)
|
||||
#define WCD937X_DIGITAL_PIN_CTL_OE (WCD937X_BASE_ADDRESS+0x4A1)
|
||||
#define WCD937X_DIGITAL_PIN_CTL_DATA_0 (WCD937X_BASE_ADDRESS+0x4A2)
|
||||
#define WCD937X_DIGITAL_PIN_CTL_DATA_1 (WCD937X_BASE_ADDRESS+0x4A3)
|
||||
#define WCD937X_DIGITAL_PIN_STATUS_0 (WCD937X_BASE_ADDRESS+0x4A4)
|
||||
#define WCD937X_DIGITAL_PIN_STATUS_1 (WCD937X_BASE_ADDRESS+0x4A5)
|
||||
#define WCD937X_DIGITAL_DIG_DEBUG_CTL (WCD937X_BASE_ADDRESS+0x4A6)
|
||||
#define WCD937X_DIGITAL_DIG_DEBUG_EN (WCD937X_BASE_ADDRESS+0x4A7)
|
||||
#define WCD937X_DIGITAL_ANA_CSR_DBG_ADD (WCD937X_BASE_ADDRESS+0x4A8)
|
||||
#define WCD937X_DIGITAL_ANA_CSR_DBG_CTL (WCD937X_BASE_ADDRESS+0x4A9)
|
||||
#define WCD937X_DIGITAL_SSP_DBG (WCD937X_BASE_ADDRESS+0x4AA)
|
||||
#define WCD937X_DIGITAL_MODE_STATUS_0 (WCD937X_BASE_ADDRESS+0x4AB)
|
||||
#define WCD937X_DIGITAL_MODE_STATUS_1 (WCD937X_BASE_ADDRESS+0x4AC)
|
||||
#define WCD937X_DIGITAL_SPARE_0 (WCD937X_BASE_ADDRESS+0x4AD)
|
||||
#define WCD937X_DIGITAL_SPARE_1 (WCD937X_BASE_ADDRESS+0x4AE)
|
||||
#define WCD937X_DIGITAL_SPARE_2 (WCD937X_BASE_ADDRESS+0x4AF)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_0 (WCD937X_BASE_ADDRESS+0x4B0)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_1 (WCD937X_BASE_ADDRESS+0x4B1)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_2 (WCD937X_BASE_ADDRESS+0x4B2)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_3 (WCD937X_BASE_ADDRESS+0x4B3)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_4 (WCD937X_BASE_ADDRESS+0x4B4)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_5 (WCD937X_BASE_ADDRESS+0x4B5)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_6 (WCD937X_BASE_ADDRESS+0x4B6)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_7 (WCD937X_BASE_ADDRESS+0x4B7)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_8 (WCD937X_BASE_ADDRESS+0x4B8)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_9 (WCD937X_BASE_ADDRESS+0x4B9)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_10 (WCD937X_BASE_ADDRESS+0x4BA)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_11 (WCD937X_BASE_ADDRESS+0x4BB)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_12 (WCD937X_BASE_ADDRESS+0x4BC)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_13 (WCD937X_BASE_ADDRESS+0x4BD)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_14 (WCD937X_BASE_ADDRESS+0x4BE)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_15 (WCD937X_BASE_ADDRESS+0x4BF)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_16 (WCD937X_BASE_ADDRESS+0x4C0)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_17 (WCD937X_BASE_ADDRESS+0x4C1)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_18 (WCD937X_BASE_ADDRESS+0x4C2)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_19 (WCD937X_BASE_ADDRESS+0x4C3)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_20 (WCD937X_BASE_ADDRESS+0x4C4)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_21 (WCD937X_BASE_ADDRESS+0x4C5)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_22 (WCD937X_BASE_ADDRESS+0x4C6)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_23 (WCD937X_BASE_ADDRESS+0x4C7)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_24 (WCD937X_BASE_ADDRESS+0x4C8)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_25 (WCD937X_BASE_ADDRESS+0x4C9)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_26 (WCD937X_BASE_ADDRESS+0x4CA)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_27 (WCD937X_BASE_ADDRESS+0x4CB)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_28 (WCD937X_BASE_ADDRESS+0x4CC)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_29 (WCD937X_BASE_ADDRESS+0x4CD)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_30 (WCD937X_BASE_ADDRESS+0x4CE)
|
||||
#define WCD937X_DIGITAL_EFUSE_REG_31 (WCD937X_BASE_ADDRESS+0x4CF)
|
||||
|
||||
#define WCD937X_REGISTERS_MAX_SIZE (WCD937X_BASE_ADDRESS+0x4D0)
|
||||
#define WCD937X_MAX_REGISTER (WCD937X_REGISTERS_MAX_SIZE - 1)
|
||||
|
||||
#endif
|
||||
462
asoc/codecs/wcd937x/wcd937x-regmap.c
Normal file
462
asoc/codecs/wcd937x/wcd937x-regmap.c
Normal file
|
|
@ -0,0 +1,462 @@
|
|||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/device.h>
|
||||
#include "wcd937x-registers.h"
|
||||
|
||||
extern const u8 wcd937x_reg_access[WCD937X_REGISTERS_MAX_SIZE];
|
||||
|
||||
static const struct reg_default wcd937x_defaults[] = {
|
||||
{ WCD937X_ANA_BIAS, 0x00 },
|
||||
{ WCD937X_ANA_RX_SUPPLIES, 0x00 },
|
||||
{ WCD937X_ANA_HPH, 0x0C },
|
||||
{ WCD937X_ANA_EAR, 0x00 },
|
||||
{ WCD937X_ANA_EAR_COMPANDER_CTL, 0x02 },
|
||||
{ WCD937X_ANA_TX_CH1, 0x20 },
|
||||
{ WCD937X_ANA_TX_CH2, 0x00 },
|
||||
{ WCD937X_ANA_TX_CH3, 0x20 },
|
||||
{ WCD937X_ANA_TX_CH3_HPF, 0x00 },
|
||||
{ WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00 },
|
||||
{ WCD937X_ANA_MICB3_DSP_EN_LOGIC, 0x00 },
|
||||
{ WCD937X_ANA_MBHC_MECH, 0x39 },
|
||||
{ WCD937X_ANA_MBHC_ELECT, 0x08 },
|
||||
{ WCD937X_ANA_MBHC_ZDET, 0x00 },
|
||||
{ WCD937X_ANA_MBHC_RESULT_1, 0x00 },
|
||||
{ WCD937X_ANA_MBHC_RESULT_2, 0x00 },
|
||||
{ WCD937X_ANA_MBHC_RESULT_3, 0x00 },
|
||||
{ WCD937X_ANA_MBHC_BTN0, 0x00 },
|
||||
{ WCD937X_ANA_MBHC_BTN1, 0x10 },
|
||||
{ WCD937X_ANA_MBHC_BTN2, 0x20 },
|
||||
{ WCD937X_ANA_MBHC_BTN3, 0x30 },
|
||||
{ WCD937X_ANA_MBHC_BTN4, 0x40 },
|
||||
{ WCD937X_ANA_MBHC_BTN5, 0x50 },
|
||||
{ WCD937X_ANA_MBHC_BTN6, 0x60 },
|
||||
{ WCD937X_ANA_MBHC_BTN7, 0x70 },
|
||||
{ WCD937X_ANA_MICB1, 0x10 },
|
||||
{ WCD937X_ANA_MICB2, 0x10 },
|
||||
{ WCD937X_ANA_MICB2_RAMP, 0x00 },
|
||||
{ WCD937X_ANA_MICB3, 0x10 },
|
||||
{ WCD937X_BIAS_CTL, 0x2A },
|
||||
{ WCD937X_BIAS_VBG_FINE_ADJ, 0x55 },
|
||||
{ WCD937X_LDOL_VDDCX_ADJUST, 0x01 },
|
||||
{ WCD937X_LDOL_DISABLE_LDOL, 0x00 },
|
||||
{ WCD937X_MBHC_CTL_CLK, 0x00 },
|
||||
{ WCD937X_MBHC_CTL_ANA, 0x00 },
|
||||
{ WCD937X_MBHC_CTL_SPARE_1, 0x00 },
|
||||
{ WCD937X_MBHC_CTL_SPARE_2, 0x00 },
|
||||
{ WCD937X_MBHC_CTL_BCS, 0x00 },
|
||||
{ WCD937X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00 },
|
||||
{ WCD937X_MBHC_TEST_CTL, 0x00 },
|
||||
{ WCD937X_LDOH_MODE, 0x2B },
|
||||
{ WCD937X_LDOH_BIAS, 0x68 },
|
||||
{ WCD937X_LDOH_STB_LOADS, 0x00 },
|
||||
{ WCD937X_LDOH_SLOWRAMP, 0x50 },
|
||||
{ WCD937X_MICB1_TEST_CTL_1, 0x1A },
|
||||
{ WCD937X_MICB1_TEST_CTL_2, 0x18 },
|
||||
{ WCD937X_MICB1_TEST_CTL_3, 0xA4 },
|
||||
{ WCD937X_MICB2_TEST_CTL_1, 0x1A },
|
||||
{ WCD937X_MICB2_TEST_CTL_2, 0x18 },
|
||||
{ WCD937X_MICB2_TEST_CTL_3, 0xA4 },
|
||||
{ WCD937X_MICB3_TEST_CTL_1, 0x1A },
|
||||
{ WCD937X_MICB3_TEST_CTL_2, 0x18 },
|
||||
{ WCD937X_MICB3_TEST_CTL_3, 0xA4 },
|
||||
{ WCD937X_TX_COM_ADC_VCM, 0x39 },
|
||||
{ WCD937X_TX_COM_BIAS_ATEST, 0xC0 },
|
||||
{ WCD937X_TX_COM_ADC_INT1_IB, 0x6F },
|
||||
{ WCD937X_TX_COM_ADC_INT2_IB, 0x4F },
|
||||
{ WCD937X_TX_COM_TXFE_DIV_CTL, 0x2E },
|
||||
{ WCD937X_TX_COM_TXFE_DIV_START, 0x00 },
|
||||
{ WCD937X_TX_COM_TXFE_DIV_STOP_9P6M, 0xC7 },
|
||||
{ WCD937X_TX_COM_TXFE_DIV_STOP_12P288M, 0xFF },
|
||||
{ WCD937X_TX_1_2_TEST_EN, 0xCC },
|
||||
{ WCD937X_TX_1_2_ADC_IB, 0x09 },
|
||||
{ WCD937X_TX_1_2_ATEST_REFCTL, 0x0A },
|
||||
{ WCD937X_TX_1_2_TEST_CTL, 0x38 },
|
||||
{ WCD937X_TX_1_2_TEST_BLK_EN, 0xFF },
|
||||
{ WCD937X_TX_1_2_TXFE_CLKDIV, 0x00 },
|
||||
{ WCD937X_TX_1_2_SAR2_ERR, 0x00 },
|
||||
{ WCD937X_TX_1_2_SAR1_ERR, 0x00 },
|
||||
{ WCD937X_TX_3_TEST_EN, 0xCC },
|
||||
{ WCD937X_TX_3_ADC_IB, 0x09 },
|
||||
{ WCD937X_TX_3_ATEST_REFCTL, 0x0A },
|
||||
{ WCD937X_TX_3_TEST_CTL, 0x38 },
|
||||
{ WCD937X_TX_3_TEST_BLK_EN, 0xFF },
|
||||
{ WCD937X_TX_3_TXFE_CLKDIV, 0x00 },
|
||||
{ WCD937X_TX_3_SPARE_MONO, 0x00 },
|
||||
{ WCD937X_TX_3_SAR1_ERR, 0x00 },
|
||||
{ WCD937X_CLASSH_MODE_1, 0x40 },
|
||||
{ WCD937X_CLASSH_MODE_2, 0x3A },
|
||||
{ WCD937X_CLASSH_MODE_3, 0x00 },
|
||||
{ WCD937X_CLASSH_CTRL_VCL_1, 0x70 },
|
||||
{ WCD937X_CLASSH_CTRL_VCL_2, 0x82 },
|
||||
{ WCD937X_CLASSH_CTRL_CCL_1, 0x31 },
|
||||
{ WCD937X_CLASSH_CTRL_CCL_2, 0x80 },
|
||||
{ WCD937X_CLASSH_CTRL_CCL_3, 0x80 },
|
||||
{ WCD937X_CLASSH_CTRL_CCL_4, 0x51 },
|
||||
{ WCD937X_CLASSH_CTRL_CCL_5, 0x00 },
|
||||
{ WCD937X_CLASSH_BUCK_TMUX_A_D, 0x00 },
|
||||
{ WCD937X_CLASSH_BUCK_SW_DRV_CNTL, 0x77 },
|
||||
{ WCD937X_CLASSH_SPARE, 0x00 },
|
||||
{ WCD937X_FLYBACK_EN, 0x4E },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_1, 0x0B },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_2, 0x45 },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_3, 0x74 },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_4, 0x7F },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_5, 0x83 },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_6, 0x98 },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_7, 0xA9 },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_8, 0x68 },
|
||||
{ WCD937X_FLYBACK_VNEG_CTRL_9, 0x64 },
|
||||
{ WCD937X_FLYBACK_VNEGDAC_CTRL_1, 0xED },
|
||||
{ WCD937X_FLYBACK_VNEGDAC_CTRL_2, 0xF0 },
|
||||
{ WCD937X_FLYBACK_VNEGDAC_CTRL_3, 0xA6 },
|
||||
{ WCD937X_FLYBACK_CTRL_1, 0x65 },
|
||||
{ WCD937X_FLYBACK_TEST_CTL, 0x00 },
|
||||
{ WCD937X_RX_AUX_SW_CTL, 0x00 },
|
||||
{ WCD937X_RX_PA_AUX_IN_CONN, 0x00 },
|
||||
{ WCD937X_RX_TIMER_DIV, 0x32 },
|
||||
{ WCD937X_RX_OCP_CTL, 0x1F },
|
||||
{ WCD937X_RX_OCP_COUNT, 0x77 },
|
||||
{ WCD937X_RX_BIAS_EAR_DAC, 0xA0 },
|
||||
{ WCD937X_RX_BIAS_EAR_AMP, 0xAA },
|
||||
{ WCD937X_RX_BIAS_HPH_LDO, 0xA9 },
|
||||
{ WCD937X_RX_BIAS_HPH_PA, 0xAA },
|
||||
{ WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A },
|
||||
{ WCD937X_RX_BIAS_HPH_RDAC_LDO, 0x88 },
|
||||
{ WCD937X_RX_BIAS_HPH_CNP1, 0x82 },
|
||||
{ WCD937X_RX_BIAS_HPH_LOWPOWER, 0x82 },
|
||||
{ WCD937X_RX_BIAS_AUX_DAC, 0xA0 },
|
||||
{ WCD937X_RX_BIAS_AUX_AMP, 0xAA },
|
||||
{ WCD937X_RX_BIAS_VNEGDAC_BLEEDER, 0x50 },
|
||||
{ WCD937X_RX_BIAS_MISC, 0x00 },
|
||||
{ WCD937X_RX_BIAS_BUCK_RST, 0x08 },
|
||||
{ WCD937X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44 },
|
||||
{ WCD937X_RX_BIAS_FLYB_ERRAMP, 0x40 },
|
||||
{ WCD937X_RX_BIAS_FLYB_BUFF, 0xAA },
|
||||
{ WCD937X_RX_BIAS_FLYB_MID_RST, 0x14 },
|
||||
{ WCD937X_HPH_L_STATUS, 0x04 },
|
||||
{ WCD937X_HPH_R_STATUS, 0x04 },
|
||||
{ WCD937X_HPH_CNP_EN, 0x80 },
|
||||
{ WCD937X_HPH_CNP_WG_CTL, 0x9A },
|
||||
{ WCD937X_HPH_CNP_WG_TIME, 0x14 },
|
||||
{ WCD937X_HPH_OCP_CTL, 0x28 },
|
||||
{ WCD937X_HPH_AUTO_CHOP, 0x16 },
|
||||
{ WCD937X_HPH_CHOP_CTL, 0x83 },
|
||||
{ WCD937X_HPH_PA_CTL1, 0x46 },
|
||||
{ WCD937X_HPH_PA_CTL2, 0x50 },
|
||||
{ WCD937X_HPH_L_EN, 0x80 },
|
||||
{ WCD937X_HPH_L_TEST, 0xE0 },
|
||||
{ WCD937X_HPH_L_ATEST, 0x50 },
|
||||
{ WCD937X_HPH_R_EN, 0x80 },
|
||||
{ WCD937X_HPH_R_TEST, 0xE0 },
|
||||
{ WCD937X_HPH_R_ATEST, 0x54 },
|
||||
{ WCD937X_HPH_RDAC_CLK_CTL1, 0x99 },
|
||||
{ WCD937X_HPH_RDAC_CLK_CTL2, 0x9B },
|
||||
{ WCD937X_HPH_RDAC_LDO_CTL, 0x33 },
|
||||
{ WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00 },
|
||||
{ WCD937X_HPH_REFBUFF_UHQA_CTL, 0xA8 },
|
||||
{ WCD937X_HPH_REFBUFF_LP_CTL, 0x0E },
|
||||
{ WCD937X_HPH_L_DAC_CTL, 0x20 },
|
||||
{ WCD937X_HPH_R_DAC_CTL, 0x20 },
|
||||
{ WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55 },
|
||||
{ WCD937X_HPH_SURGE_HPHLR_SURGE_EN, 0x19 },
|
||||
{ WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0 },
|
||||
{ WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00 },
|
||||
{ WCD937X_EAR_EAR_EN_REG, 0x22 },
|
||||
{ WCD937X_EAR_EAR_PA_CON, 0x44 },
|
||||
{ WCD937X_EAR_EAR_SP_CON, 0xDB },
|
||||
{ WCD937X_EAR_EAR_DAC_CON, 0x80 },
|
||||
{ WCD937X_EAR_EAR_CNP_FSM_CON, 0xB2 },
|
||||
{ WCD937X_EAR_TEST_CTL, 0x00 },
|
||||
{ WCD937X_EAR_STATUS_REG_1, 0x00 },
|
||||
{ WCD937X_EAR_STATUS_REG_2, 0x00 },
|
||||
{ WCD937X_ANA_NEW_PAGE_REGISTER, 0x00 },
|
||||
{ WCD937X_HPH_NEW_ANA_HPH2, 0x00 },
|
||||
{ WCD937X_HPH_NEW_ANA_HPH3, 0x00 },
|
||||
{ WCD937X_SLEEP_CTL, 0x16 },
|
||||
{ WCD937X_SLEEP_WATCHDOG_CTL, 0x00 },
|
||||
{ WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00 },
|
||||
{ WCD937X_MBHC_NEW_CTL_1, 0x02 },
|
||||
{ WCD937X_MBHC_NEW_CTL_2, 0x05 },
|
||||
{ WCD937X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9 },
|
||||
{ WCD937X_MBHC_NEW_ZDET_ANA_CTL, 0x0F },
|
||||
{ WCD937X_MBHC_NEW_ZDET_RAMP_CTL, 0x00 },
|
||||
{ WCD937X_MBHC_NEW_FSM_STATUS, 0x00 },
|
||||
{ WCD937X_MBHC_NEW_ADC_RESULT, 0x00 },
|
||||
{ WCD937X_TX_NEW_TX_CH2_SEL, 0x00 },
|
||||
{ WCD937X_AUX_AUXPA, 0x00 },
|
||||
{ WCD937X_LDORXTX_MODE, 0x0C },
|
||||
{ WCD937X_LDORXTX_CONFIG, 0x10 },
|
||||
{ WCD937X_DIE_CRACK_DIE_CRK_DET_EN, 0x00 },
|
||||
{ WCD937X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00 },
|
||||
{ WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40 },
|
||||
{ WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81 },
|
||||
{ WCD937X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10 },
|
||||
{ WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00 },
|
||||
{ WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81 },
|
||||
{ WCD937X_HPH_NEW_INT_PA_MISC1, 0x22 },
|
||||
{ WCD937X_HPH_NEW_INT_PA_MISC2, 0x00 },
|
||||
{ WCD937X_HPH_NEW_INT_PA_RDAC_MISC, 0x00 },
|
||||
{ WCD937X_HPH_NEW_INT_HPH_TIMER1, 0xFE },
|
||||
{ WCD937X_HPH_NEW_INT_HPH_TIMER2, 0x02 },
|
||||
{ WCD937X_HPH_NEW_INT_HPH_TIMER3, 0x4E },
|
||||
{ WCD937X_HPH_NEW_INT_HPH_TIMER4, 0x54 },
|
||||
{ WCD937X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00 },
|
||||
{ WCD937X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00 },
|
||||
{ WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62 },
|
||||
{ WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01 },
|
||||
{ WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11 },
|
||||
{ WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57 },
|
||||
{ WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01 },
|
||||
{ WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00 },
|
||||
{ WCD937X_MBHC_NEW_INT_SPARE_2, 0x00 },
|
||||
{ WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8 },
|
||||
{ WCD937X_EAR_INT_NEW_CNP_VCM_CON1, 0x42 },
|
||||
{ WCD937X_EAR_INT_NEW_CNP_VCM_CON2, 0x22 },
|
||||
{ WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00 },
|
||||
{ WCD937X_AUX_INT_EN_REG, 0x00 },
|
||||
{ WCD937X_AUX_INT_PA_CTRL, 0x06 },
|
||||
{ WCD937X_AUX_INT_SP_CTRL, 0xD2 },
|
||||
{ WCD937X_AUX_INT_DAC_CTRL, 0x80 },
|
||||
{ WCD937X_AUX_INT_CLK_CTRL, 0x50 },
|
||||
{ WCD937X_AUX_INT_TEST_CTRL, 0x00 },
|
||||
{ WCD937X_AUX_INT_STATUS_REG, 0x00 },
|
||||
{ WCD937X_AUX_INT_MISC, 0x00 },
|
||||
{ WCD937X_LDORXTX_INT_BIAS, 0x6E },
|
||||
{ WCD937X_LDORXTX_INT_STB_LOADS_DTEST, 0x50 },
|
||||
{ WCD937X_LDORXTX_INT_TEST0, 0x1C },
|
||||
{ WCD937X_LDORXTX_INT_STARTUP_TIMER, 0xFF },
|
||||
{ WCD937X_LDORXTX_INT_TEST1, 0x1F },
|
||||
{ WCD937X_LDORXTX_INT_STATUS, 0x00 },
|
||||
{ WCD937X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A },
|
||||
{ WCD937X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A },
|
||||
{ WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02 },
|
||||
{ WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60 },
|
||||
{ WCD937X_DIGITAL_PAGE_REGISTER, 0x00 },
|
||||
{ WCD937X_DIGITAL_CHIP_ID0, 0x00 },
|
||||
{ WCD937X_DIGITAL_CHIP_ID1, 0x00 },
|
||||
{ WCD937X_DIGITAL_CHIP_ID2, 0x0A },
|
||||
{ WCD937X_DIGITAL_CHIP_ID3, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_RST_CTL, 0x03 },
|
||||
{ WCD937X_DIGITAL_TOP_CLK_CFG, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_ANA_CLK_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_SWR_RST_EN, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_PATH_MODE, 0x55 },
|
||||
{ WCD937X_DIGITAL_CDC_RX_RST, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_RX0_CTL, 0xFC },
|
||||
{ WCD937X_DIGITAL_CDC_RX1_CTL, 0xFC },
|
||||
{ WCD937X_DIGITAL_CDC_RX2_CTL, 0xFC },
|
||||
{ WCD937X_DIGITAL_DEM_BYPASS_DATA0, 0x55 },
|
||||
{ WCD937X_DIGITAL_DEM_BYPASS_DATA1, 0x55 },
|
||||
{ WCD937X_DIGITAL_DEM_BYPASS_DATA2, 0x55 },
|
||||
{ WCD937X_DIGITAL_DEM_BYPASS_DATA3, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_COMP_CTL_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_RX_DELAY_CTL, 0x66 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_C_0, 0x47 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_C_1, 0x43 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_C_3, 0x17 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_R1, 0x4B },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_R2, 0x27 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_R3, 0x32 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_R4, 0x57 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_R4, 0x63 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_R4, 0x7C },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_DSM_R4, 0x57 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_C_0, 0x69 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_C_1, 0x54 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_C_2, 0x02 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_C_3, 0x15 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_R1, 0xA4 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_R2, 0xB5 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_R3, 0x86 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_R4, 0x85 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_R5, 0xAA },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_R6, 0xE2 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_DSM_R7, 0x62 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_EAR_PATH_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_SWR_CLH, 0x00 },
|
||||
{ WCD937X_DIGITAL_SWR_CLH_BYP, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_TX0_CTL, 0x68 },
|
||||
{ WCD937X_DIGITAL_CDC_TX1_CTL, 0x68 },
|
||||
{ WCD937X_DIGITAL_CDC_TX2_CTL, 0x68 },
|
||||
{ WCD937X_DIGITAL_CDC_TX_RST, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_REQ_CTL, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_AMIC_CTL, 0x07 },
|
||||
{ WCD937X_DIGITAL_CDC_DMIC_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_DMIC0_CTL, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_DMIC1_CTL, 0x01 },
|
||||
{ WCD937X_DIGITAL_CDC_DMIC2_CTL, 0x01 },
|
||||
{ WCD937X_DIGITAL_EFUSE_CTL, 0x2B },
|
||||
{ WCD937X_DIGITAL_EFUSE_PRG_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_TEST_CTL_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_TEST_CTL_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_T_DATA_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_T_DATA_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_PDM_WD_CTL0, 0x00 },
|
||||
{ WCD937X_DIGITAL_PDM_WD_CTL1, 0x00 },
|
||||
{ WCD937X_DIGITAL_PDM_WD_CTL2, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_MODE, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_MASK_0, 0xFF },
|
||||
{ WCD937X_DIGITAL_INTR_MASK_1, 0xFF },
|
||||
{ WCD937X_DIGITAL_INTR_MASK_2, 0xFF },
|
||||
{ WCD937X_DIGITAL_INTR_STATUS_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_STATUS_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_STATUS_2, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_CLEAR_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_CLEAR_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_CLEAR_2, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_LEVEL_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_LEVEL_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_LEVEL_2, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_SET_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_SET_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_SET_2, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_TEST_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_TEST_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_INTR_TEST_2, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_CONN_RX0_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_CONN_RX1_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_CONN_RX2_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_CDC_CONN_TX_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_LOOP_BACK_MODE, 0x00 },
|
||||
{ WCD937X_DIGITAL_SWR_DAC_TEST, 0x00 },
|
||||
{ WCD937X_DIGITAL_SWR_HM_TEST_RX_0, 0x40 },
|
||||
{ WCD937X_DIGITAL_SWR_HM_TEST_TX_0, 0x40 },
|
||||
{ WCD937X_DIGITAL_SWR_HM_TEST_RX_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_SWR_HM_TEST_TX_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_SWR_HM_TEST, 0x00 },
|
||||
{ WCD937X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1 },
|
||||
{ WCD937X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1 },
|
||||
{ WCD937X_DIGITAL_PAD_CTL_PDM_RX2, 0xF1 },
|
||||
{ WCD937X_DIGITAL_PAD_CTL_PDM_TX, 0xF1 },
|
||||
{ WCD937X_DIGITAL_PAD_INP_DIS_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_DRIVE_STRENGTH_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_DRIVE_STRENGTH_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_DRIVE_STRENGTH_2, 0x00 },
|
||||
{ WCD937X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F },
|
||||
{ WCD937X_DIGITAL_TX_DATA_EDGE_CTL, 0x10 },
|
||||
{ WCD937X_DIGITAL_GPIO_MODE, 0x00 },
|
||||
{ WCD937X_DIGITAL_PIN_CTL_OE, 0x00 },
|
||||
{ WCD937X_DIGITAL_PIN_CTL_DATA_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_PIN_CTL_DATA_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_PIN_STATUS_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_PIN_STATUS_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_DIG_DEBUG_CTL, 0x00 },
|
||||
{ WCD937X_DIGITAL_DIG_DEBUG_EN, 0x00 },
|
||||
{ WCD937X_DIGITAL_ANA_CSR_DBG_ADD, 0x00 },
|
||||
{ WCD937X_DIGITAL_ANA_CSR_DBG_CTL, 0x48 },
|
||||
{ WCD937X_DIGITAL_SSP_DBG, 0x00 },
|
||||
{ WCD937X_DIGITAL_MODE_STATUS_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_MODE_STATUS_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_SPARE_0, 0x00 },
|
||||
{ WCD937X_DIGITAL_SPARE_1, 0x00 },
|
||||
{ WCD937X_DIGITAL_SPARE_2, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_0, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_1, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_2, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_3, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_4, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_5, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_6, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_7, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_8, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_9, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_10, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_11, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_12, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_13, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_14, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_15, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_16, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_17, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_18, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_19, 0xFF },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_20, 0x0E },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_21, 0x8F },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_22, 0x16 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_23, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_24, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_25, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_26, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_27, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_28, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_29, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_30, 0x00 },
|
||||
{ WCD937X_DIGITAL_EFUSE_REG_31, 0x00 },
|
||||
};
|
||||
|
||||
static bool wcd937x_readable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
return wcd937x_reg_access[WCD937X_REG(reg)] & RD_REG;
|
||||
}
|
||||
|
||||
static bool wcd937x_writeable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
return wcd937x_reg_access[WCD937X_REG(reg)] & WR_REG;
|
||||
}
|
||||
|
||||
static bool wcd937x_volatile_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
return (wcd937x_reg_access[WCD937X_REG(reg)] & RD_REG)
|
||||
& ~(wcd937x_reg_access[WCD937X_REG(reg)] & WR_REG);
|
||||
}
|
||||
|
||||
struct regmap_config wcd937x_regmap_config = {
|
||||
.reg_bits = 16,
|
||||
.val_bits = 8,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.reg_defaults = wcd937x_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(wcd937x_defaults),
|
||||
.max_register = WCD937X_MAX_REGISTER,
|
||||
.readable_reg = wcd937x_readable_register,
|
||||
.writeable_reg = wcd937x_writeable_register,
|
||||
.volatile_reg = wcd937x_volatile_register,
|
||||
.can_multi_write = true,
|
||||
};
|
||||
432
asoc/codecs/wcd937x/wcd937x-tables.c
Normal file
432
asoc/codecs/wcd937x/wcd937x-tables.c
Normal file
|
|
@ -0,0 +1,432 @@
|
|||
/*
|
||||
* Copyright (c) 2018 , The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "wcd937x-registers.h"
|
||||
|
||||
const u8 wcd937x_reg_access[WCD937X_REG(WCD937X_REGISTERS_MAX_SIZE)] = {
|
||||
[WCD937X_REG(WCD937X_ANA_BIAS)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_RX_SUPPLIES)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_HPH)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_EAR)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_EAR_COMPANDER_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_TX_CH1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_TX_CH2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_TX_CH3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_TX_CH3_HPF)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MICB3_DSP_EN_LOGIC)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_MECH)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_ELECT)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_ZDET)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_RESULT_1)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_RESULT_2)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_RESULT_3)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_BTN0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_BTN1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_BTN2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_BTN3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_BTN4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_BTN5)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_BTN6)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MBHC_BTN7)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MICB1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MICB2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MICB2_RAMP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_MICB3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_BIAS_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_BIAS_VBG_FINE_ADJ)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDOL_VDDCX_ADJUST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDOL_DISABLE_LDOL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_CTL_CLK)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_CTL_ANA)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_CTL_SPARE_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_CTL_SPARE_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_CTL_BCS)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_MOISTURE_DET_FSM_STATUS)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_TEST_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDOH_MODE)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDOH_BIAS)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDOH_STB_LOADS)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDOH_SLOWRAMP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB1_TEST_CTL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB1_TEST_CTL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB1_TEST_CTL_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB2_TEST_CTL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB2_TEST_CTL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB2_TEST_CTL_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB3_TEST_CTL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB3_TEST_CTL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MICB3_TEST_CTL_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_COM_ADC_VCM)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_COM_BIAS_ATEST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_COM_ADC_INT1_IB)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_COM_ADC_INT2_IB)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_COM_TXFE_DIV_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_COM_TXFE_DIV_START)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_COM_TXFE_DIV_STOP_9P6M)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_COM_TXFE_DIV_STOP_12P288M)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_1_2_TEST_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_1_2_ADC_IB)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_1_2_ATEST_REFCTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_1_2_TEST_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_1_2_TEST_BLK_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_1_2_TXFE_CLKDIV)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_1_2_SAR2_ERR)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_TX_1_2_SAR1_ERR)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_TX_3_TEST_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_3_ADC_IB)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_3_ATEST_REFCTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_3_TEST_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_3_TEST_BLK_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_3_TXFE_CLKDIV)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_TX_3_SPARE_MONO)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_TX_3_SAR1_ERR)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_MODE_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_MODE_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_MODE_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_CTRL_VCL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_CTRL_VCL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_CTRL_CCL_5)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_BUCK_TMUX_A_D)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_BUCK_SW_DRV_CNTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_CLASSH_SPARE)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_5)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_6)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_7)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_8)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEG_CTRL_9)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEGDAC_CTRL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEGDAC_CTRL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_VNEGDAC_CTRL_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_CTRL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_FLYBACK_TEST_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_AUX_SW_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_PA_AUX_IN_CONN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_TIMER_DIV)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_OCP_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_OCP_COUNT)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_EAR_DAC)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_EAR_AMP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_HPH_LDO)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_HPH_PA)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_HPH_RDAC_LDO)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_HPH_CNP1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_HPH_LOWPOWER)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_AUX_DAC)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_AUX_AMP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_VNEGDAC_BLEEDER)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_MISC)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_BUCK_RST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_BUCK_VREF_ERRAMP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_FLYB_ERRAMP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_FLYB_BUFF)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_BIAS_FLYB_MID_RST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_L_STATUS)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_R_STATUS)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_CNP_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_CNP_WG_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_CNP_WG_TIME)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_OCP_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_AUTO_CHOP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_CHOP_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_PA_CTL1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_PA_CTL2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_L_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_L_TEST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_L_ATEST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_R_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_R_TEST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_R_ATEST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_RDAC_CLK_CTL1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_RDAC_CLK_CTL2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_RDAC_LDO_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_REFBUFF_UHQA_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_REFBUFF_LP_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_L_DAC_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_R_DAC_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_SURGE_HPHLR_SURGE_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_EAR_EN_REG)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_EAR_PA_CON)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_EAR_SP_CON)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_EAR_DAC_CON)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_EAR_CNP_FSM_CON)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_TEST_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_STATUS_REG_1)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_STATUS_REG_2)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_ANA_NEW_PAGE_REGISTER)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_ANA_HPH2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_ANA_HPH3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_SLEEP_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_SLEEP_WATCHDOG_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_CTL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_CTL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_PLUG_DETECT_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_ZDET_ANA_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_ZDET_RAMP_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_FSM_STATUS)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_ADC_RESULT)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_TX_NEW_TX_CH2_SEL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_AUXPA)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDORXTX_MODE)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDORXTX_CONFIG)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIE_CRACK_DIE_CRK_DET_EN)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIE_CRACK_DIE_CRK_DET_OUT)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_VREF_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_MISC1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_MISC2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_RDAC_MISC)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_HPH_TIMER1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_HPH_TIMER2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_HPH_TIMER3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_HPH_TIMER4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_RDAC_MISC2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_HPH_NEW_INT_PA_RDAC_MISC3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL)]
|
||||
= RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_MBHC_NEW_INT_SPARE_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_INT_NEW_CNP_VCM_CON1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_INT_NEW_CNP_VCM_CON2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_INT_EN_REG)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_INT_PA_CTRL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_INT_SP_CTRL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_INT_DAC_CTRL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_INT_CLK_CTRL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_INT_TEST_CTRL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_INT_STATUS_REG)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_AUX_INT_MISC)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDORXTX_INT_BIAS)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDORXTX_INT_STB_LOADS_DTEST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDORXTX_INT_TEST0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDORXTX_INT_STARTUP_TIMER)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDORXTX_INT_TEST1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_LDORXTX_INT_STATUS)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_SLEEP_INT_WATCHDOG_CTL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_SLEEP_INT_WATCHDOG_CTL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PAGE_REGISTER)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CHIP_ID0)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CHIP_ID1)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CHIP_ID2)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CHIP_ID3)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_RST_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_TOP_CLK_CFG)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_ANA_CLK_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_DIG_CLK_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SWR_RST_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_PATH_MODE)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_RX_RST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_RX0_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_RX1_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_RX2_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DEM_BYPASS_DATA0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DEM_BYPASS_DATA1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DEM_BYPASS_DATA2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DEM_BYPASS_DATA3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_COMP_CTL_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_RX_DELAY_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A1_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A1_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A2_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A2_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A3_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A3_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A4_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A4_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A5_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A5_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A6_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_A7_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_C_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_C_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_C_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_C_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_DSM_R4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A1_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A1_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A2_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A2_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A3_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A3_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A4_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A4_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A5_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A5_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A6_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_A7_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_C_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_C_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_C_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_C_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R5)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R6)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_DSM_R7)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_HPH_GAIN_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AUX_GAIN_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_EAR_PATH_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_SWR_CLH)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SWR_CLH_BYP)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_TX0_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_TX1_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_TX2_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_TX_RST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_REQ_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_AMIC_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_DMIC_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_DMIC0_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_DMIC1_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_DMIC2_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_PRG_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_TEST_CTL_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_TEST_CTL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_T_DATA_0)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_T_DATA_1)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PDM_WD_CTL0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PDM_WD_CTL1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PDM_WD_CTL2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_MODE)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_MASK_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_MASK_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_MASK_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_STATUS_0)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_STATUS_1)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_STATUS_2)] = RD_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_CLEAR_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_CLEAR_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_CLEAR_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_LEVEL_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_LEVEL_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_LEVEL_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_SET_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_SET_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_SET_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_TEST_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_TEST_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_INTR_TEST_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_CONN_RX0_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_CONN_RX1_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_CONN_RX2_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_CDC_CONN_TX_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_LOOP_BACK_MODE)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SWR_DAC_TEST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST_RX_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST_TX_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST_RX_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST_TX_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SWR_HM_TEST)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_RX0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_RX1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_RX2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_TX)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PAD_CTL_PDM_TX)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PAD_INP_DIS_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DRIVE_STRENGTH_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DRIVE_STRENGTH_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DRIVE_STRENGTH_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_RX_DATA_EDGE_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_TX_DATA_EDGE_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_GPIO_MODE)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PIN_CTL_OE)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PIN_CTL_DATA_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PIN_CTL_DATA_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PIN_STATUS_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_PIN_STATUS_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DIG_DEBUG_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_DIG_DEBUG_EN)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_ANA_CSR_DBG_ADD)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_ANA_CSR_DBG_CTL)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SSP_DBG)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_MODE_STATUS_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_MODE_STATUS_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SPARE_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SPARE_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_SPARE_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_0)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_1)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_2)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_3)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_4)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_5)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_6)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_7)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_8)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_9)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_10)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_11)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_12)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_13)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_14)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_15)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_16)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_17)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_18)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_19)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_20)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_21)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_22)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_23)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_24)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_25)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_26)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_27)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_28)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_29)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_30)] = RD_WR_REG,
|
||||
[WCD937X_REG(WCD937X_DIGITAL_EFUSE_REG_31)] = RD_WR_REG,
|
||||
};
|
||||
File diff suppressed because it is too large
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Reference in a new issue