MIPS: XLR, XLS: Add PCI support.
Adds pci/pci-xlr.c to support for XLR PCI/PCI-X interface and XLS PCIe interface. Update irq.c to ack PCI interrupts, use irq handler data to do the PCI/PCIe bus ack. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2337/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jayachandran C
Ralf Baechle
parent
f9cab74fd9
commit
9b130f8004
4 changed files with 321 additions and 1 deletions
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@ -41,6 +41,7 @@ unsigned int nlm_xlr_uart_in(struct uart_port *, int);
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void nlm_xlr_uart_out(struct uart_port *, int, int);
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/* SMP support functions */
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struct irq_desc;
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void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
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int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
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@ -51,4 +52,24 @@ void prom_pre_boot_secondary_cpus(void);
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extern struct plat_smp_ops nlm_smp_ops;
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extern unsigned long nlm_common_ebase;
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/* XLS B silicon "Rook" */
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static inline unsigned int nlm_chip_is_xls_b(void)
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{
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uint32_t prid = read_c0_prid();
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return ((prid & 0xf000) == 0x4000);
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}
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/*
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* XLR chip types
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*/
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/* The XLS product line has chip versions 0x[48c]? */
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static inline unsigned int nlm_chip_is_xls(void)
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{
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uint32_t prid = read_c0_prid();
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return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
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(prid & 0xf000) == 0xc000);
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}
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#endif /* _ASM_NLM_XLR_H */
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@ -83,14 +83,71 @@ static void xlr_pic_mask(struct irq_data *d)
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spin_unlock_irqrestore(&nlm_pic_lock, flags);
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}
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#ifdef CONFIG_PCI
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/* Extra ACK needed for XLR on chip PCI controller */
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static void xlr_pci_ack(struct irq_data *d)
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{
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nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
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netlogic_read_reg(pci_mmio, (0x140 >> 2));
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}
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/* Extra ACK needed for XLS on chip PCIe controller */
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static void xls_pcie_ack(struct irq_data *d)
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{
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nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
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switch (d->irq) {
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case PIC_PCIE_LINK0_IRQ:
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netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
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break;
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case PIC_PCIE_LINK1_IRQ:
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netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
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break;
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case PIC_PCIE_LINK2_IRQ:
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netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
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break;
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case PIC_PCIE_LINK3_IRQ:
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netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
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break;
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}
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}
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/* For XLS B silicon, the 3,4 PCI interrupts are different */
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static void xls_pcie_ack_b(struct irq_data *d)
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{
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nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
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switch (d->irq) {
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case PIC_PCIE_LINK0_IRQ:
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netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
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break;
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case PIC_PCIE_LINK1_IRQ:
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netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
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break;
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case PIC_PCIE_XLSB0_LINK2_IRQ:
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netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
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break;
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case PIC_PCIE_XLSB0_LINK3_IRQ:
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netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
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break;
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}
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}
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#endif
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static void xlr_pic_ack(struct irq_data *d)
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{
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unsigned long flags;
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nlm_reg_t *mmio;
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int irq = d->irq;
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void *hd = irq_data_get_irq_handler_data(d);
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WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
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if (hd) {
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void (*extra_ack)(void *) = hd;
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extra_ack(d);
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}
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mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
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spin_lock_irqsave(&nlm_pic_lock, flags);
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netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
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@ -162,6 +219,33 @@ void __init init_xlr_irqs(void)
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nlm_irq_mask |=
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((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
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#endif
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#ifdef CONFIG_PCI
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/*
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* For PCI interrupts, we need to ack the PIC controller too, overload
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* irq handler data to do this
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*/
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if (nlm_chip_is_xls()) {
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if (nlm_chip_is_xls_b()) {
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irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
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xls_pcie_ack_b);
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irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
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xls_pcie_ack_b);
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irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
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xls_pcie_ack_b);
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irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
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xls_pcie_ack_b);
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} else {
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irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
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irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
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irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
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irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
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}
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} else {
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/* XLR PCI controller ACK */
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irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
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}
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#endif
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/* unmask all PIC related interrupts. If no handler is installed by the
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* drivers, it'll just ack the interrupt and return
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*/
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@ -199,7 +283,7 @@ asmlinkage void plat_irq_dispatch(void)
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return;
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}
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/* TODO use dcltz: optimize below code */
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/* use dcltz: optimize below code */
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for (i = 63; i != -1; i--) {
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if (eirr & (1ULL << i))
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break;
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@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
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obj-$(CONFIG_NLM_XLR) += pci-xlr.o
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ifdef CONFIG_PCI_MSI
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
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214
arch/mips/pci/pci-xlr.c
Normal file
214
arch/mips/pci/pci-xlr.c
Normal file
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@ -0,0 +1,214 @@
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/console.h>
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#include <asm/io.h>
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#include <asm/netlogic/interrupt.h>
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#include <asm/netlogic/xlr/iomap.h>
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#include <asm/netlogic/xlr/pic.h>
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#include <asm/netlogic/xlr/xlr.h>
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static void *pci_config_base;
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#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
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/* PCI ops */
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static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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u32 data;
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u32 *cfgaddr;
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cfgaddr = (u32 *)(pci_config_base +
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pci_cfg_addr(bus->number, devfn, where & ~3));
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data = *cfgaddr;
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return cpu_to_le32(data);
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}
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static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
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int where, u32 data)
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{
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u32 *cfgaddr;
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cfgaddr = (u32 *)(pci_config_base +
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pci_cfg_addr(bus->number, devfn, where & ~3));
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*cfgaddr = cpu_to_le32(data);
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}
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static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 data;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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data = pci_cfg_read_32bit(bus, devfn, where);
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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data = pci_cfg_read_32bit(bus, devfn, where);
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else
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data = val;
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pci_cfg_write_32bit(bus, devfn, where, data);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops nlm_pci_ops = {
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.read = nlm_pcibios_read,
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.write = nlm_pcibios_write
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};
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static struct resource nlm_pci_mem_resource = {
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.name = "XLR PCI MEM",
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.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
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.end = 0xdfffffffUL,
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.flags = IORESOURCE_MEM,
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};
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static struct resource nlm_pci_io_resource = {
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.name = "XLR IO MEM",
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.start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
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.end = 0x100fffffUL,
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.flags = IORESOURCE_IO,
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};
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struct pci_controller nlm_pci_controller = {
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.index = 0,
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.pci_ops = &nlm_pci_ops,
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.mem_resource = &nlm_pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &nlm_pci_io_resource,
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.io_offset = 0x00000000UL,
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};
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (!nlm_chip_is_xls())
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return PIC_PCIX_IRQ; /* for XLR just one IRQ*/
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/*
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* For XLS PCIe, there is an IRQ per Link, find out which
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* link the device is on to assign interrupts
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*/
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if (dev->bus->self == NULL)
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return 0;
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switch (dev->bus->self->devfn) {
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case 0x0:
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return PIC_PCIE_LINK0_IRQ;
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case 0x8:
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return PIC_PCIE_LINK1_IRQ;
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case 0x10:
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if (nlm_chip_is_xls_b())
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return PIC_PCIE_XLSB0_LINK2_IRQ;
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else
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return PIC_PCIE_LINK2_IRQ;
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case 0x18:
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if (nlm_chip_is_xls_b())
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return PIC_PCIE_XLSB0_LINK3_IRQ;
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else
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return PIC_PCIE_LINK3_IRQ;
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}
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WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
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return 0;
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static int __init pcibios_init(void)
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{
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/* PSB assigns PCI resources */
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pci_probe_only = 1;
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pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
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/* Extend IO port for memory mapped io */
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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set_io_port_base(CKSEG1);
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nlm_pci_controller.io_map_base = CKSEG1;
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pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
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register_pci_controller(&nlm_pci_controller);
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return 0;
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}
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arch_initcall(pcibios_init);
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struct pci_fixup pcibios_fixups[] = {
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{0}
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};
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