video: exynos_dp: Improve EDID error handling
EDID error handling has 2 problems: - It doesn't fail as early as it can - The retry counts for i2c and aux transactions are huge This patch fails if the initial i2c transaction fails, and reduces the aux and i2c retry counts down to 3. [jg1.han@samsung.com: reduced the retry count of exynos_dp_read_byte_from_dpcd()] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
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2 changed files with 14 additions and 13 deletions
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@ -91,9 +91,11 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
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*/
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*/
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/* Read Extension Flag, Number of 128-byte EDID extension blocks */
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/* Read Extension Flag, Number of 128-byte EDID extension blocks */
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exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
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retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
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EDID_EXTENSION_FLAG,
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EDID_EXTENSION_FLAG,
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&extend_block);
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&extend_block);
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if (retval)
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return retval;
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if (extend_block > 0) {
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if (extend_block > 0) {
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dev_dbg(dp->dev, "EDID data includes a single extension!\n");
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dev_dbg(dp->dev, "EDID data includes a single extension!\n");
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@ -182,14 +184,15 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
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int retval;
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int retval;
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/* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
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/* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
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exynos_dp_read_bytes_from_dpcd(dp,
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retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV,
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DPCD_ADDR_DPCD_REV,
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12, buf);
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12, buf);
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if (retval)
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return retval;
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/* Read EDID */
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/* Read EDID */
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for (i = 0; i < 3; i++) {
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for (i = 0; i < 3; i++) {
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retval = exynos_dp_read_edid(dp);
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retval = exynos_dp_read_edid(dp);
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if (retval == 0)
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if (!retval)
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break;
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break;
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}
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}
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@ -491,7 +491,7 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
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int i;
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int i;
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int retval;
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int retval;
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 3; i++) {
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/* Clear AUX CH data buffer */
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/* Clear AUX CH data buffer */
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reg = BUF_CLR;
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reg = BUF_CLR;
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writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
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writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
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@ -552,7 +552,7 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
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else
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else
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cur_data_count = count - start_offset;
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cur_data_count = count - start_offset;
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 3; i++) {
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/* Select DPCD device address */
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/* Select DPCD device address */
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reg = AUX_ADDR_7_0(reg_addr + start_offset);
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reg = AUX_ADDR_7_0(reg_addr + start_offset);
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writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
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writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
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@ -617,7 +617,7 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
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cur_data_count = count - start_offset;
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cur_data_count = count - start_offset;
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/* AUX CH Request Transaction process */
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/* AUX CH Request Transaction process */
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 3; i++) {
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/* Select DPCD device address */
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/* Select DPCD device address */
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reg = AUX_ADDR_7_0(reg_addr + start_offset);
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reg = AUX_ADDR_7_0(reg_addr + start_offset);
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writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
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writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
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@ -700,17 +700,15 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
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int i;
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int i;
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int retval;
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int retval;
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 3; i++) {
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/* Clear AUX CH data buffer */
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/* Clear AUX CH data buffer */
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reg = BUF_CLR;
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reg = BUF_CLR;
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writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
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writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
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/* Select EDID device */
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/* Select EDID device */
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retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
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retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
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if (retval != 0) {
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if (retval != 0)
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dev_err(dp->dev, "Select EDID device fail!\n");
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continue;
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continue;
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}
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/*
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/*
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* Set I2C transaction and read data
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* Set I2C transaction and read data
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@ -750,7 +748,7 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
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int retval = 0;
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int retval = 0;
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for (i = 0; i < count; i += 16) {
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for (i = 0; i < count; i += 16) {
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for (j = 0; j < 100; j++) {
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for (j = 0; j < 3; j++) {
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/* Clear AUX CH data buffer */
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/* Clear AUX CH data buffer */
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reg = BUF_CLR;
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reg = BUF_CLR;
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writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
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writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
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