soundwire: Add bank switch routine
SoundWire supports two registers banks. So, program the alternate bank with new configuration and then performs bank switch. Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com> Signed-off-by: Shreyas NC <shreyas.nc@intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sanyog Kale
Vinod Koul
parent
79df15b7d3
commit
99b8a5d608
4 changed files with 262 additions and 0 deletions
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@ -78,6 +78,13 @@ int sdw_add_bus_master(struct sdw_bus *bus)
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return ret;
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}
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/*
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* Default active bank will be 0 as out of reset the Slaves have
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* to start with bank 0 (Table 40 of Spec)
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*/
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bus->params.curr_bank = SDW_BANK0;
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bus->params.next_bank = SDW_BANK1;
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return 0;
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}
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EXPORT_SYMBOL(sdw_add_bus_master);
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@ -45,6 +45,11 @@ struct sdw_msg {
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bool page;
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};
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#define SDW_DOUBLE_RATE_FACTOR 2
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extern int rows[SDW_FRAME_ROWS];
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extern int cols[SDW_FRAME_COLS];
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/**
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* sdw_port_runtime: Runtime port parameters for Master or Slave
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*
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@ -15,6 +15,43 @@
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#include <linux/soundwire/sdw.h>
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#include "bus.h"
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/*
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* Array of supported rows and columns as per MIPI SoundWire Specification 1.1
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*
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* The rows are arranged as per the array index value programmed
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* in register. The index 15 has dummy value 0 in order to fill hole.
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*/
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int rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
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96, 100, 120, 128, 150, 160, 250, 0,
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192, 200, 240, 256, 72, 144, 90, 180};
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int cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
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static int sdw_find_col_index(int col)
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{
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int i;
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for (i = 0; i < SDW_FRAME_COLS; i++) {
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if (cols[i] == col)
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return i;
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}
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pr_warn("Requested column not found, selecting lowest column no: 2\n");
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return 0;
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}
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static int sdw_find_row_index(int row)
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{
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int i;
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for (i = 0; i < SDW_FRAME_ROWS; i++) {
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if (rows[i] == row)
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return i;
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}
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pr_warn("Requested row not found, selecting lowest row no: 48\n");
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return 0;
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}
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static int _sdw_program_slave_port_params(struct sdw_bus *bus,
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struct sdw_slave *slave,
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struct sdw_transport_params *t_params,
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@ -514,6 +551,171 @@ static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
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return ret;
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}
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/**
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* sdw_notify_config() - Notify bus configuration
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*
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* @m_rt: Master runtime handle
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*
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* This function notifies the Master(s) and Slave(s) of the
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* new bus configuration.
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*/
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static int sdw_notify_config(struct sdw_master_runtime *m_rt)
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{
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struct sdw_slave_runtime *s_rt;
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struct sdw_bus *bus = m_rt->bus;
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struct sdw_slave *slave;
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int ret = 0;
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if (bus->ops->set_bus_conf) {
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ret = bus->ops->set_bus_conf(bus, &bus->params);
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if (ret < 0)
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return ret;
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}
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list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
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slave = s_rt->slave;
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if (slave->ops->bus_config) {
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ret = slave->ops->bus_config(slave, &bus->params);
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if (ret < 0)
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dev_err(bus->dev, "Notify Slave: %d failed",
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slave->dev_num);
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return ret;
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}
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}
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return ret;
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}
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/**
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* sdw_program_params() - Program transport and port parameters for Master(s)
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* and Slave(s)
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*
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* @bus: SDW bus instance
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*/
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static int sdw_program_params(struct sdw_bus *bus)
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{
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struct sdw_master_runtime *m_rt = NULL;
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int ret = 0;
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list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
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ret = sdw_program_port_params(m_rt);
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if (ret < 0) {
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dev_err(bus->dev,
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"Program transport params failed: %d", ret);
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return ret;
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}
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ret = sdw_notify_config(m_rt);
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if (ret < 0) {
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dev_err(bus->dev, "Notify bus config failed: %d", ret);
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return ret;
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}
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/* Enable port(s) on alternate bank for all active streams */
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if (m_rt->stream->state != SDW_STREAM_ENABLED)
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continue;
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ret = sdw_enable_disable_ports(m_rt, true);
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if (ret < 0) {
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dev_err(bus->dev, "Enable channel failed: %d", ret);
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return ret;
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}
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}
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return ret;
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}
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static int sdw_bank_switch(struct sdw_bus *bus)
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{
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int col_index, row_index;
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struct sdw_msg *wr_msg;
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u8 *wbuf = NULL;
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int ret = 0;
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u16 addr;
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wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
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if (!wr_msg)
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return -ENOMEM;
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wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
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if (!wbuf) {
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ret = -ENOMEM;
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goto error_1;
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}
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/* Get row and column index to program register */
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col_index = sdw_find_col_index(bus->params.col);
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row_index = sdw_find_row_index(bus->params.row);
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wbuf[0] = col_index | (row_index << 3);
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if (bus->params.next_bank)
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addr = SDW_SCP_FRAMECTRL_B1;
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else
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addr = SDW_SCP_FRAMECTRL_B0;
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sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
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SDW_MSG_FLAG_WRITE, wbuf);
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wr_msg->ssp_sync = true;
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ret = sdw_transfer(bus, wr_msg);
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if (ret < 0) {
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dev_err(bus->dev, "Slave frame_ctrl reg write failed");
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goto error;
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}
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kfree(wr_msg);
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kfree(wbuf);
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bus->defer_msg.msg = NULL;
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bus->params.curr_bank = !bus->params.curr_bank;
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bus->params.next_bank = !bus->params.next_bank;
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return 0;
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error:
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kfree(wbuf);
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error_1:
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kfree(wr_msg);
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return ret;
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}
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static int do_bank_switch(struct sdw_stream_runtime *stream)
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{
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struct sdw_master_runtime *m_rt = stream->m_rt;
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const struct sdw_master_ops *ops;
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struct sdw_bus *bus = m_rt->bus;
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int ret = 0;
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ops = bus->ops;
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/* Pre-bank switch */
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if (ops->pre_bank_switch) {
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ret = ops->pre_bank_switch(bus);
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if (ret < 0) {
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dev_err(bus->dev, "Pre bank switch op failed: %d", ret);
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return ret;
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}
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}
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/* Bank switch */
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ret = sdw_bank_switch(bus);
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if (ret < 0) {
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dev_err(bus->dev, "Bank switch failed: %d", ret);
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return ret;
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}
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/* Post-bank switch */
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if (ops->post_bank_switch) {
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ret = ops->post_bank_switch(bus);
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if (ret < 0) {
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dev_err(bus->dev,
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"Post bank switch op failed: %d", ret);
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}
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}
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return ret;
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}
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/**
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* sdw_release_stream() - Free the assigned stream runtime
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*
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@ -23,7 +23,17 @@ struct sdw_slave;
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#define SDW_MASTER_DEV_NUM 14
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#define SDW_NUM_DEV_ID_REGISTERS 6
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/* frame shape defines */
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/*
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* Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
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* fill hole with 0, one more dummy entry is added
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*/
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#define SDW_FRAME_ROWS 24
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#define SDW_FRAME_COLS 8
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#define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
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#define SDW_FRAME_CTRL_BITS 48
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#define SDW_MAX_DEVICES 11
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#define SDW_VALID_PORT_RANGE(n) (n <= 14 && n >= 1)
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@ -376,6 +386,21 @@ enum sdw_reg_bank {
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SDW_BANK1,
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};
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/**
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* struct sdw_bus_conf: Bus configuration
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*
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* @clk_freq: Clock frequency, in Hz
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* @num_rows: Number of rows in frame
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* @num_cols: Number of columns in frame
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* @bank: Next register bank
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*/
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struct sdw_bus_conf {
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unsigned int clk_freq;
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unsigned int num_rows;
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unsigned int num_cols;
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unsigned int bank;
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};
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/**
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* struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
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*
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@ -413,10 +438,20 @@ enum sdw_port_prep_ops {
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* @curr_bank: Current bank in use (BANK0/BANK1)
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* @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
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* set to !curr_bank
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* @max_dr_freq: Maximum double rate clock frequency supported, in Hz
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* @curr_dr_freq: Current double rate clock frequency, in Hz
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* @bandwidth: Current bandwidth
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* @col: Active columns
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* @row: Active rows
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*/
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struct sdw_bus_params {
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enum sdw_reg_bank curr_bank;
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enum sdw_reg_bank next_bank;
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unsigned int max_dr_freq;
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unsigned int curr_dr_freq;
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unsigned int bandwidth;
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unsigned int col;
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unsigned int row;
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};
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/**
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@ -426,6 +461,7 @@ struct sdw_bus_params {
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* @interrupt_callback: Device interrupt notification (invoked in thread
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* context)
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* @update_status: Update Slave status
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* @bus_config: Update the bus config for Slave
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* @port_prep: Prepare the port with parameters
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*/
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struct sdw_slave_ops {
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@ -434,6 +470,8 @@ struct sdw_slave_ops {
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struct sdw_slave_intr_status *status);
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int (*update_status)(struct sdw_slave *slave,
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enum sdw_slave_status status);
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int (*bus_config)(struct sdw_slave *slave,
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struct sdw_bus_params *params);
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int (*port_prep)(struct sdw_slave *slave,
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struct sdw_prepare_ch *prepare_ch,
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enum sdw_port_prep_ops pre_ops);
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@ -597,6 +635,9 @@ struct sdw_defer {
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* @xfer_msg: Transfer message callback
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* @xfer_msg_defer: Defer version of transfer message callback
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* @reset_page_addr: Reset the SCP page address registers
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* @set_bus_conf: Set the bus configuration
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* @pre_bank_switch: Callback for pre bank switch
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* @post_bank_switch: Callback for post bank switch
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*/
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struct sdw_master_ops {
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int (*read_prop)(struct sdw_bus *bus);
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@ -608,6 +649,11 @@ struct sdw_master_ops {
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struct sdw_defer *defer);
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enum sdw_command_response (*reset_page_addr)
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(struct sdw_bus *bus, unsigned int dev_num);
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int (*set_bus_conf)(struct sdw_bus *bus,
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struct sdw_bus_params *params);
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int (*pre_bank_switch)(struct sdw_bus *bus);
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int (*post_bank_switch)(struct sdw_bus *bus);
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};
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/**
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@ -628,6 +674,7 @@ struct sdw_master_ops {
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* transport and port parameters
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* @defer_msg: Defer message
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* @clk_stop_timeout: Clock stop timeout computed
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* @bank_switch_timeout: Bank switch timeout computed
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*/
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struct sdw_bus {
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struct device *dev;
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@ -643,6 +690,7 @@ struct sdw_bus {
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struct list_head m_rt_list;
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struct sdw_defer defer_msg;
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unsigned int clk_stop_timeout;
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u32 bank_switch_timeout;
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};
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int sdw_add_bus_master(struct sdw_bus *bus);
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