X86 platform: New BayTrail IOSF-SB MBI driver
Current Intel SOC cores use a MailBox Interface (MBI) to provide access to unit devices connected to the system fabric. This driver implements access to this interface on BayTrail platforms. This is a requirement for drivers that need access to unit registers on the platform (e.g. accessing the PUNIT for power management features such as RAPL). Serialized access is handled by all exported routines with spinlocks. The API includes 3 functions for access to unit registers: int bt_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr) int bt_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr) int bt_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) port: indicating the unit being accessed opcode: the read or write port specific opcode offset: the register offset within the port mdr: the register data to be read, written, or modified mask: bit locations in mdr to change Returns nonzero on error Note: GPU code handles access to the GFX unit. Therefore access to that unit with this driver is disallowed to avoid conflicts. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com>
This commit is contained in:
David E. Box
Matthew Garrett
parent
475879d651
commit
997ab407d2
4 changed files with 323 additions and 0 deletions
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@ -808,4 +808,12 @@ config PVPANIC
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a paravirtualized device provided by QEMU; it lets a virtual machine
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(guest) communicate panic events to the host.
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config INTEL_BAYTRAIL_MBI
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tristate
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depends on PCI
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---help---
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Needed on Baytrail platforms for access to the IOSF Sideband Mailbox
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Interface. This is a requirement for systems that need to configure
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the PUNIT for power management features such as RAPL.
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endif # X86_PLATFORM_DEVICES
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@ -54,3 +54,4 @@ obj-$(CONFIG_INTEL_RST) += intel-rst.o
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obj-$(CONFIG_INTEL_SMARTCONNECT) += intel-smartconnect.o
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obj-$(CONFIG_PVPANIC) += pvpanic.o
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obj-$(CONFIG_INTEL_BAYTRAIL_MBI) += intel_baytrail.o
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224
drivers/platform/x86/intel_baytrail.c
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224
drivers/platform/x86/intel_baytrail.c
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@ -0,0 +1,224 @@
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/*
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* Baytrail IOSF-SB MailBox Interface Driver
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* Copyright (c) 2013, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*
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* The IOSF-SB is a fabric bus available on Atom based SOC's that uses a
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* mailbox interface (MBI) to communicate with mutiple devices. This
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* driver implements BayTrail-specific access to this interface.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include "intel_baytrail.h"
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static DEFINE_SPINLOCK(iosf_mbi_lock);
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static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
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{
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return (op << 24) | (port << 16) | (offset << 8) | BT_MBI_ENABLE;
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}
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static struct pci_dev *mbi_pdev; /* one mbi device */
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/* Hold lock before calling */
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static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
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{
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int result;
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if (!mbi_pdev)
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return -ENODEV;
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if (mcrx) {
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result = pci_write_config_dword(mbi_pdev,
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BT_MBI_MCRX_OFFSET, mcrx);
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if (result < 0)
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goto iosf_mbi_read_err;
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}
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result = pci_write_config_dword(mbi_pdev,
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BT_MBI_MCR_OFFSET, mcr);
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if (result < 0)
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goto iosf_mbi_read_err;
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result = pci_read_config_dword(mbi_pdev,
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BT_MBI_MDR_OFFSET, mdr);
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if (result < 0)
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goto iosf_mbi_read_err;
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return 0;
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iosf_mbi_read_err:
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dev_err(&mbi_pdev->dev, "error: PCI config operation returned %d\n",
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result);
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return result;
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}
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/* Hold lock before calling */
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static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr)
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{
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int result;
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if (!mbi_pdev)
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return -ENODEV;
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result = pci_write_config_dword(mbi_pdev,
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BT_MBI_MDR_OFFSET, mdr);
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if (result < 0)
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goto iosf_mbi_write_err;
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if (mcrx) {
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result = pci_write_config_dword(mbi_pdev,
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BT_MBI_MCRX_OFFSET, mcrx);
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if (result < 0)
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goto iosf_mbi_write_err;
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}
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result = pci_write_config_dword(mbi_pdev,
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BT_MBI_MCR_OFFSET, mcr);
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if (result < 0)
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goto iosf_mbi_write_err;
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return 0;
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iosf_mbi_write_err:
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dev_err(&mbi_pdev->dev, "error: PCI config operation returned %d\n",
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result);
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return result;
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}
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int bt_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
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{
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u32 mcr, mcrx;
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unsigned long flags;
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int ret;
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/*Access to the GFX unit is handled by GPU code */
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BUG_ON(port == BT_MBI_UNIT_GFX);
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mcr = iosf_mbi_form_mcr(opcode, port, offset & BT_MBI_MASK_LO);
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mcrx = offset & BT_MBI_MASK_HI;
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spin_lock_irqsave(&iosf_mbi_lock, flags);
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ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
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spin_unlock_irqrestore(&iosf_mbi_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(bt_mbi_read);
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int bt_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
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{
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u32 mcr, mcrx;
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unsigned long flags;
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int ret;
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/*Access to the GFX unit is handled by GPU code */
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BUG_ON(port == BT_MBI_UNIT_GFX);
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mcr = iosf_mbi_form_mcr(opcode, port, offset & BT_MBI_MASK_LO);
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mcrx = offset & BT_MBI_MASK_HI;
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spin_lock_irqsave(&iosf_mbi_lock, flags);
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ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
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spin_unlock_irqrestore(&iosf_mbi_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(bt_mbi_write);
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int bt_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
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{
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u32 mcr, mcrx;
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u32 value;
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unsigned long flags;
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int ret;
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/*Access to the GFX unit is handled by GPU code */
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BUG_ON(port == BT_MBI_UNIT_GFX);
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mcr = iosf_mbi_form_mcr(opcode, port, offset & BT_MBI_MASK_LO);
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mcrx = offset & BT_MBI_MASK_HI;
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spin_lock_irqsave(&iosf_mbi_lock, flags);
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/* Read current mdr value */
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ret = iosf_mbi_pci_read_mdr(mcrx, mcr & BT_MBI_RD_MASK, &value);
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if (ret < 0) {
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spin_unlock_irqrestore(&iosf_mbi_lock, flags);
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return ret;
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}
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/* Apply mask */
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value &= ~mask;
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mdr &= mask;
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value |= mdr;
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/* Write back */
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ret = iosf_mbi_pci_write_mdr(mcrx, mcr | BT_MBI_WR_MASK, value);
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spin_unlock_irqrestore(&iosf_mbi_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(bt_mbi_modify);
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static int iosf_mbi_probe(struct pci_dev *pdev,
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const struct pci_device_id *unused)
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{
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int ret;
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ret = pci_enable_device(pdev);
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if (ret < 0) {
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dev_err(&pdev->dev, "error: could not enable device\n");
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return ret;
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}
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mbi_pdev = pci_dev_get(pdev);
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return 0;
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}
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static DEFINE_PCI_DEVICE_TABLE(iosf_mbi_pci_ids) = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0F00) },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
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static struct pci_driver iosf_mbi_pci_driver = {
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.name = "iosf_mbi_pci",
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.probe = iosf_mbi_probe,
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.id_table = iosf_mbi_pci_ids,
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};
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static int __init bt_mbi_init(void)
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{
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return pci_register_driver(&iosf_mbi_pci_driver);
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}
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static void __exit bt_mbi_exit(void)
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{
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pci_unregister_driver(&iosf_mbi_pci_driver);
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if (mbi_pdev) {
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pci_dev_put(mbi_pdev);
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mbi_pdev = NULL;
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}
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}
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module_init(bt_mbi_init);
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module_exit(bt_mbi_exit);
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MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
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MODULE_DESCRIPTION("BayTrail Mailbox Interface accessor");
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MODULE_LICENSE("GPL v2");
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90
drivers/platform/x86/intel_baytrail.h
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90
drivers/platform/x86/intel_baytrail.h
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@ -0,0 +1,90 @@
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/*
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* intel_baytrail.h: MailBox access support for Intel BayTrail platforms
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*/
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#ifndef INTEL_BAYTRAIL_MBI_SYMS_H
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#define INTEL_BAYTRAIL_MBI_SYMS_H
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#define BT_MBI_MCR_OFFSET 0xD0
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#define BT_MBI_MDR_OFFSET 0xD4
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#define BT_MBI_MCRX_OFFSET 0xD8
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#define BT_MBI_RD_MASK 0xFEFFFFFF
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#define BT_MBI_WR_MASK 0X01000000
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#define BT_MBI_MASK_HI 0xFFFFFF00
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#define BT_MBI_MASK_LO 0x000000FF
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#define BT_MBI_ENABLE 0xF0
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/* BT-SB unit access methods */
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#define BT_MBI_UNIT_AUNIT 0x00
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#define BT_MBI_UNIT_SMC 0x01
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#define BT_MBI_UNIT_CPU 0x02
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#define BT_MBI_UNIT_BUNIT 0x03
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#define BT_MBI_UNIT_PMC 0x04
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#define BT_MBI_UNIT_GFX 0x06
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#define BT_MBI_UNIT_SMI 0x0C
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#define BT_MBI_UNIT_USB 0x43
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#define BT_MBI_UNIT_SATA 0xA3
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#define BT_MBI_UNIT_PCIE 0xA6
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/* Read/write opcodes */
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#define BT_MBI_AUNIT_READ 0x10
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#define BT_MBI_AUNIT_WRITE 0x11
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#define BT_MBI_SMC_READ 0x10
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#define BT_MBI_SMC_WRITE 0x11
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#define BT_MBI_CPU_READ 0x10
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#define BT_MBI_CPU_WRITE 0x11
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#define BT_MBI_BUNIT_READ 0x10
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#define BT_MBI_BUNIT_WRITE 0x11
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#define BT_MBI_PMC_READ 0x06
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#define BT_MBI_PMC_WRITE 0x07
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#define BT_MBI_GFX_READ 0x00
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#define BT_MBI_GFX_WRITE 0x01
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#define BT_MBI_SMIO_READ 0x06
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#define BT_MBI_SMIO_WRITE 0x07
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#define BT_MBI_USB_READ 0x06
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#define BT_MBI_USB_WRITE 0x07
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#define BT_MBI_SATA_READ 0x00
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#define BT_MBI_SATA_WRITE 0x01
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#define BT_MBI_PCIE_READ 0x00
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#define BT_MBI_PCIE_WRITE 0x01
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/**
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* bt_mbi_read() - MailBox Interface read command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data to be read
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int bt_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
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/**
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* bt_mbi_write() - MailBox unmasked write command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data to be written
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int bt_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
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/**
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* bt_mbi_modify() - MailBox masked write command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data being modified
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* @mask: mask indicating bits in mdr to be modified
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int bt_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
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#endif /* INTEL_BAYTRAIL_MBI_SYMS_H */
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