Techwizz/kernel-fxtec-pro1x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

[MIPS] Ocelot: remove remaining bits

Browse source 
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yoichi Yuasa 2007-09-06 21:32:57 +09:00 committed by Ralf Baechle
parent d6698a2cd6
commit 98f9085405
2 changed files with 0 additions and 44 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
arch/mips/Kconfig
View file

@ -818,20 +818,6 @@ config EMMA2RH
config SERIAL_RM9000 config SERIAL_RM9000
bool bool
#
# Unfortunately not all GT64120 systems run the chip at the same clock.
# As the user for the clock rate and try to minimize the available options.
#
choice
prompt "Galileo Chip Clock"
depends on MOMENCO_OCELOT
default SYSCLK_100 if MOMENCO_OCELOT
config SYSCLK_100
bool "100" if MOMENCO_OCELOT
endchoice
config ARC32 config ARC32
bool bool

30
include/asm-mips/mach-ocelot/mach-gt64120.h
View file

@ -1,30 +0,0 @@
/*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H
/*
* PCI address allocation
*/
#define GT_PCI_MEM_BASE (0x22000000UL)
#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE
#define GT_PCI_IO_BASE (0x20000000UL)
#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE
extern unsigned long gt64120_base;
#define GT64120_BASE (gt64120_base)
/*
* GT timer irq
*/
#define GT_TIMER 6
#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */